Semiconductor Memory Device Erase Efficiency via Initial Setting Voltage
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Solution Overview
Problem
Nonvolatile semiconductor memory devices have lower read and write speeds compared to volatile devices, which can hinder their performance in applications requiring data retention regardless of power supply status, and existing three-dimensional semiconductor devices face limitations in integration and erase efficiency.
Innovation Solution
A semiconductor memory device with a memory cell array, voltage generator, and control logic that applies an initial setting voltage to bit lines before an erase voltage is applied to the source line during an erase operation, improving erase efficiency by reducing potential level differences and enhancing hot hole formation for efficient data erasure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If three-dimensional semiconductor device structure is used to improve integration degree, then integration capability is improved, but erase efficiency deteriorates due to potential level differences between bit lines and source lines
Solution Approach 1:
The patent applies preliminary action by setting the potential level of bit lines to a reference level before applying erase voltage to source lines. This preliminary potential level adjustment ensures that when erase voltage is subsequently applied, the potential difference between bit lines and source lines is optimized, enabling efficient hot hole generation and electron-trap charge removal without compromising the three-dimensional vertical string structure's integration benefits
Solution Approach 2:
The patent changes the electrical parameter (potential level) of bit lines from a conventional state to a reference level state before erase operation. This parameter change creates optimal conditions for erase efficiency by ensuring appropriate potential difference between bit lines and source lines during voltage application, while maintaining the integrated three-dimensional device architecture
2Device complexity
If conventional erase operation is used in three-dimensional device, then device complexity is reduced, but erase efficiency deteriorates due to insufficient hot hole formation
Solution Approach 1:
The patent introduces a preliminary step before conventional erase operation where the potential level of bit lines is set to a reference level. This preliminary action prepares the electrical conditions necessary for efficient hot hole formation when erase voltage is subsequently applied to source lines, thereby improving erase efficiency without significantly complicating the overall device structure or operation sequence
Solution Approach 2:
The patent modifies the electrical parameters (potential levels) of bit lines and source lines during the erase operation sequence. By changing these parameters in a controlled manner - setting bit lines to reference level first, then applying erase voltage to source lines - the patent optimizes hot hole generation and electron removal efficiency while maintaining operational simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enhances erase efficiency by increasing potential levels of bit lines and source lines, improving data retention and integration capabilities in semiconductor memory devices.
Implementation Method 1
enhancing hot hole formation for efficient data erasure
Data Source
AI summary
A semiconductor memory device includes a memory cell array including a plurality of memory blocks, a voltage generator suitable for applying an erase voltage to a source line of at least one memory block selected from among the plurality of memory blocks during an erase operation, a read and write circuit suitable for applying an initial setting voltage to bit lines of at least one memory block during the erase operation, and a control logic suitable for controlling the voltage generator and the read and write circuit to apply the initial setting voltage to the bit lines before applying the erase voltage to the source line.