Semiconductor Memory Device Erase Voltage Control

Solution Overview

Problem

NAND flash memory devices face challenges in achieving efficient erase operations due to stress on cells and reduced data retention characteristics, with existing methods either requiring high erase voltages that deteriorate cells or prolonged erase times with lower voltages.

Innovation Solution

A semiconductor memory device with a control circuit that simultaneously erases multiple memory cells using a first erase voltage, performs a verify operation, and adjusts the erase voltage based on the number of cells exceeding a verify level, thereby optimizing erase speed and accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high erase voltage is applied to erase memory cells deeply, then erase completeness is improved, but cell stress increases and data retention deteriorates

Engineering Contradiction:

Improveerase completenessVSAvoidcell stress

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies periodic erase pulses with alternating high and low voltages to memory cells. The high voltage pulses provide strong erasure when needed, while low voltage pulses allow recovery and reduce cumulative stress. This periodic switching enables complete erasure without continuously exposing cells to harmful high stress levels.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent dynamically changes erase voltage parameters based on the erasure state of memory cells. By monitoring erase progress and adjusting voltage magnitude and pulse width, the system achieves effective erasure while minimizing unnecessary stress. The voltage parameters are modified in response to feedback from verify operations.

Inventive Principle:

Principle #35Parameter changes

2Object-affected harmful factors

If low erase voltage is applied to reduce cell stress, then data retention is improved, but erase time increases and multiple erase pulses are required

Engineering Contradiction:

Improvecell stressVSAvoiderase time

Core Design Contradiction:

Object-affected harmful factorsVSLoss of time

Solution Approach 1:

The patent uses periodic erase pulses with alternating high and low voltages to memory cells. The high voltage pulses provide strong erasure when needed, while low voltage pulses allow recovery and reduce cumulative stress. This periodic switching enables complete erasure without continuously exposing cells to harmful high stress levels.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent implements feedback control by performing verify operations after erase pulses and using the results to determine subsequent erase actions. This feedback mechanism prevents unnecessary repeated erase pulses by accurately detecting when erasure is complete, thereby reducing total erase time while maintaining cell health.

Inventive Principle:

Principle #23Feedback

3Reliability

If multiple erase pulses are applied gradually to erase memory cells, then erase completeness is improved, but erase time increases and cell stress accumulates

Engineering Contradiction:

Improveerase completenessVSAvoiderase time

Core Design Contradiction:

ReliabilityVSDuration of action of moving object

Solution Approach 1:

The patent uses periodic erase pulses with alternating high and low voltages to memory cells. The high voltage pulses provide strong erasure when needed, while low voltage pulses allow recovery and reduce cumulative stress. This periodic switching enables complete erasure without continuously exposing cells to harmful high stress levels.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent implements feedback control by performing verify operations after erase pulses and using the results to determine subsequent erase actions. This feedback mechanism prevents unnecessary repeated erase pulses by accurately detecting when erasure is complete, thereby reducing total erase time while maintaining cell health.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS11830559B2Semiconductor memory device capable of shortening erase time

Publication Date: 2023.11.28 KIOXIA CORP

AI summary

In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k≤n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.