Memory Array Erased-Page Checking with Adaptive Read Compensation
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Solution Overview
Problem
The integration of logic circuits to handle special situations in memory devices, such as read disturbance and power failure, enlarges the control logic area, hindering miniaturization.
Innovation Solution
A memory device with a characteristic parameter storage region and peripheral circuit that performs erased page checking operations based on received parameters, including read voltage compensation and fail bit allowance, allowing flexible operation in different scenarios without increasing circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic circuits are added to handle special situations (read disturbance detection, power failure recovery), then the reliability and functionality of the memory device are improved, but the control logic area is enlarged, hindering miniaturization
Solution Approach 1:
The patent extracts the special situation handling logic from the main control logic and implements it through software/firmware routines executed by the existing controller. Specifically, read disturbance detection and power failure recovery functions are implemented as executable instructions rather than dedicated hardware circuits, thereby removing the need for additional logic circuit area while maintaining the reliability improvements
Solution Approach 2:
The existing controller is made universal by enabling it to handle multiple functions including normal read/write operations, read disturbance detection, and power failure recovery through a single integrated control unit. This multi-functionality eliminates the need for separate dedicated circuits for each special situation, thus avoiding control logic area enlargement
2Measurement precision
If dedicated logic circuits are implemented for each special situation, then the detection accuracy and operation capability are improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent introduces an intermediary approach by using software routines as mediators between the hardware and the special situation handling requirements. The controller executes intermediary software code that implements detection algorithms for read disturbance and power failure scenarios, achieving high detection accuracy without the need for complex dedicated hardware circuits for each function
Data Source
AI summary
The present disclosure provides a memory device and an operation method thereof, a memory system and an operation method thereof, and an electronic apparatus. The memory device includes a memory array and a peripheral circuit coupled with the memory array; the peripheral circuit is configured to: in response to a characteristic parameter setting command, receive a characteristic parameter of an erased page checking operation, wherein the characteristic parameter of the erased page checking operation includes at least a read voltage compensation parameter of the erased page checking operation; and in response to an erased page checking command, perform the erased page checking operation on the memory array based on the characteristic parameter of the erased page checking operation.