Nonvolatile Memory Erasing Control via GIDL Current
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Solution Overview
Problem
The challenge in improving the bit density of nonvolatile semiconductor memory devices, such as NAND type flash memories, is the limitation of miniaturization techniques, which requires simplification of the manufacturing process to reduce costs, while maintaining effective erasing operations across multiple memory strings connected to a common word line.
Innovation Solution
A nonvolatile semiconductor memory device design that includes a control circuit capable of independently controlling erasing operations on selected and non-selected cell units within memory blocks by managing voltages and GIDL currents across multiple transistors, allowing for simultaneous erasing on selected blocks while preventing erasing on non-selected blocks, thereby optimizing manufacturing efficiency and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gates of memory transistors in multiple memory strings are connected commonly to one word line to simplify the manufacturing process, then the manufacturing complexity is reduced, but the erasing operation can only be executed simultaneously on all memory strings connected by one word line (block basis)
Solution Approach 1:
The patent introduces dummy transistors with independent word line connections to segment the erasing operation control. Each dummy transistor's word line can be independently controlled to enable or disable erasing for specific memory strings, allowing selective erasing within a block without changing the common word line connection structure of actual memory transistors.
Solution Approach 2:
The dummy transistors act as intermediary elements between the word line control circuit and the memory transistors. By controlling the dummy transistors' gate voltages, the patent can selectively enable or disable the body connection to memory transistors, thereby controlling erasing operations without directly modifying the memory transistor gate connections.
2Quantity of substance
If vertical stacking of memory transistors is implemented to improve bit density, then the bit density is increased, but the manufacturing process becomes more complex
Solution Approach 1:
The dummy transistors serve multiple functions: they act as body connection switches for erasing control, provide selective erasing capability for individual memory strings, and maintain compatibility with existing vertical stacking manufacturing processes. This multi-functionality allows the patent to achieve selective erasing in vertically stacked structures without adding significant manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances bit density and manufacturing efficiency by enabling precise control over erasing operations, reducing the risk of erroneous data loss and power consumption, while maintaining cost-effectiveness.
Implementation Method 1
an operation of generating a GIDL current by setting the voltage of the second line connected to the selected cell unit higher than the voltage of the gate of the second transistor included in the selected cell unit
Implementation Method 2
an operation of suppressing generation of a GIDL current by setting the voltage of the gate of the second transistor included in the non-selected cell unit equal to or higher than the voltage of the second line connected to the non-selected cell unit
Implementation Method 3
the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage
Data Source
AI summary
A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit.