Memory Error Correction Using Erasure-Aware Cell Sensing
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Solution Overview
Problem
Error detection and correction in resistance variable memory cells are hindered by mechanisms such as read disturb and shorts, leading to reduced performance and lifetime, especially in high-density memory devices, where existing error correction methods may fail to correct errors effectively.
Innovation Solution
Identifying and marking memory cells that cannot store data as erasures during an error correction operation, using methods like secondary sense operations, sensing circuitry with check signals, and bipolar sense operations to increase the error correction capability by distinguishing between valid and invalid data states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction methods are applied to resistance variable memory cells, then reliability is improved, but device complexity increases due to additional sense operations and marking mechanisms
Solution Approach 1:
The patent applies preliminary action by performing a first sense operation to identify and mark erasure bits before conducting the main error correction operation. This preliminary identification of invalid memory cells allows the subsequent error correction to focus only on correctable errors, improving overall reliability while managing complexity through staged processing
Solution Approach 2:
The error correction process is segmented into distinct operations: a first sense operation to detect erasures, a marking step to identify invalid bits, and a second error correction operation. This segmentation allows each component to be optimized independently, addressing reliability through comprehensive error handling while controlling device complexity through modular design
2Measurement precision
If multiple sense operations are performed to identify erasures, then measurement precision is improved, but loss of time increases due to additional sensing cycles
Solution Approach 1:
The first sense operation serves as a preliminary action that quickly identifies erasure bits without requiring full error correction processing. By separating erasure detection from error correction, the system achieves high measurement precision for identifying invalid cells while minimizing time loss through efficient staged operations
Solution Approach 2:
The patent extracts the erasure detection function from the main error correction process by performing a dedicated first sense operation. This extraction allows precise identification of erasures to be completed separately and efficiently, improving measurement precision while reducing the time burden on the overall error correction operation
3Reliability
If erasures are marked and handled separately, then reliability is improved through better error correction, but device complexity increases due to additional marking and identification circuitry
Solution Approach 1:
The marking of erasure bits is performed as a preliminary action before the main error correction operation. This preliminary marking simplifies the subsequent error correction by pre-identifying invalid bits, improving reliability through accurate error classification while managing device complexity through sequential processing
Solution Approach 2:
The patent introduces an intermediary marking mechanism that bridges erasure detection and error correction. This intermediary step uses simple marking circuitry to tag invalid bits, improving data integrity through reliable error identification while keeping device complexity manageable by using a dedicated but simplified marking layer between detection and correction operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the error correction rate by accurately identifying and correcting errors, thereby improving the raw bit error rate and extending the lifespan of memory devices.
Implementation Method 1
resistance variable memory cells that can store data based on the resistance state of a storage element (e.g., a memory element having a variable resistance)
Implementation Method 2
A state of a resistance variable memory cell can be determined by sensing current through the cell responsive to an applied interrogation voltage. The sensed current, which varies based on the resistance level of the cell, can indicate the state of the cell.
Data Source
AI summary
The present disclosure includes apparatuses, methods, and systems for error detection and correction in memory. An embodiment includes a memory having a group of self-selecting memory cells which store data corresponding to a codeword from an error correcting code, and circuitry configured to perform a sense operation on the group of self-selecting memory cells, identify, based on the sense operation, memory cells of the group that cannot store data, mark data sensed from the identified memory cells as erasures and perform an error correction operation on data sensed from the group of self-selecting memory cells with the data sensed from the identified memory cells marked as erasures.