Multi-Level Memory Error Correction Using Erasure Decoding
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Solution Overview
Problem
Existing error correction techniques in memory devices face challenges in achieving high code rates without increasing processing time and latency, particularly in correcting errors in multi-level cell memory systems.
Innovation Solution
The implementation of a tensor product code that combines constituent codes such as Single Parity Check (SPC) and Bose-Chaudhuri-Hocquenghem (BCH) codes, along with Low-Density Parity-Check (LDPC) codes, to identify and correct erroneous cells by converting them into erasures, thereby enhancing the code rate during decoding operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If higher code rates are used to improve error correction efficiency, then processing time and latency increase
Solution Approach 1:
The patent segments the error correction process into two distinct phases: a first decoding attempt using a first decoder with lower computational complexity, and a second decoding attempt using a second decoder with higher computational complexity only if the first fails. This segmentation allows the system to achieve high error correction efficiency when needed while maintaining low processing time for the majority of cases where errors are fewer or correctable by the simpler decoder.
Solution Approach 2:
The patent applies partial action by using the full computational power of high code rate decoding only when necessary (when the first decoding attempt fails), rather than always applying it. This selective application of excessive computational resources resolves the contradiction by providing high error correction efficiency only when the error conditions warrant it, while avoiding the associated processing time and latency overhead for routine operations.
2Reliability
If redundant information bits are increased to improve error correction capability, then code rate decreases and processing overhead increases
Solution Approach 1:
The patent dynamically adjusts the effective code rate by selecting between different decoding strategies based on the actual error conditions. The system starts with a higher effective code rate approach (first decoder) and only transitions to the lower code rate approach (second decoder) when errors exceed the correction capability of the first decoder. This dynamic adaptation resolves the contradiction by optimizing the balance between error correction capability and code rate based on real-time conditions.
Solution Approach 2:
The patent changes the operational parameters of the decoding process by switching between different decoders with different code rates. The system effectively varies the code rate parameter dynamically - using a higher effective code rate when possible and transitioning to a lower code rate only when error conditions necessitate the enhanced correction capability, thereby resolving the contradiction between reliability and productivity.
Data Source
AI summary
Embodiments of the present invention disclose methods and apparatuses for correcting errors in data stored in a solid state device. The solid state device may have a plurality of bits stored in multi-level memory cells. The method may include identifying one or more errors in a plurality of memory cells. The method may further include converting the erroneous cells to erasures. The method may further include correcting the one or more erasures.