Memory Error Classification for Adaptive ECC and Read Voltage
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Solution Overview
Problem
Conventional memory systems face inefficiencies in data integrity operations due to shifts in threshold voltages of memory cells, leading to increased power consumption and latency in error detection and recovery, especially when storing multiple bits of data.
Innovation Solution
A memory sub-system with a data integrity classifier that dynamically adjusts error detection and recovery operations based on error rate classification generated from signal and noise characteristics measured by the memory device, using predictive models and machine learning to select appropriate ECC decoders and read voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error detection and recovery operations are performed on all memory data, then data integrity is maintained, but power consumption increases
Solution Approach 1:
The system dynamically changes operational parameters (ECC decoder type, read voltage levels) based on the error rate classification of memory blocks. Low error rate blocks use simplified operations while high error rate blocks use enhanced error correction, optimizing the balance between data integrity and power consumption.
Solution Approach 2:
Different error detection and recovery operations are applied to different memory blocks based on their individual error rate characteristics. Instead of uniform processing, each block receives tailored operations matching its quality level, reducing unnecessary power consumption in low-error blocks.
2Reliability
If conventional error detection and recovery operations are performed on all memory data, then data integrity is maintained, but latency increases
Solution Approach 1:
The system dynamically adjusts operational parameters including selecting between different ECC decoder types and read voltage configurations based on error rate classification. This parameter adaptation reduces processing time for low-error blocks while maintaining integrity for high-error blocks.
Solution Approach 2:
For memory blocks with low error rates, the system applies partial error detection operations rather than full error correction procedures. This partial action approach maintains sufficient data integrity while significantly reducing the time required for processing these blocks.
3Quantity of substance
If threshold voltage shifts in memory cells are accommodated, then multiple bits of data can be stored, but error rate increases
Solution Approach 1:
The system performs preliminary classification of memory blocks into error rate categories before executing error detection and recovery operations. This preliminary action enables the system to prepare appropriate processing strategies in advance, addressing error-prone blocks with enhanced operations while maintaining efficiency in reliable blocks.
Solution Approach 2:
The system uses feedback from error rate classification to dynamically adjust error detection and recovery operations. The classification results feed into the operation selection process, creating a closed-loop system that adapts to the actual error characteristics of each memory block, thereby managing the trade-off between storage capacity and reliability.
Data Source
AI summary
A memory sub-system configured to dynamically select an option to process encoded data retrieved from memory cells of a memory component, based on a prediction generated using signal and noise characteristics of memory cells storing the encoded data. For example, the memory component is enclosed in an integrated circuit and has a calibration circuit. The signal and noise characteristics are measured by the calibration circuit as a byproduct of executing a read command in the memory component to retrieve the encoded data. A data integrity classifier configured in the memory sub-system generates a prediction based on the signal and noise characteristics. Based on the prediction, the memory sub-system selects an option from a plurality of options configured in the memory sub-system to process the encoded data.