Memory System with Error-Prone Address Redirection

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Solution Overview

Problem

As supply voltage reduces, the reliability of SRAM in memory modules decreases, making it challenging to maintain reliable data storage, especially in devices requiring additional voltage for security features, and existing error correction methods often result in significant overhead, reducing available storage space.

Innovation Solution

A memory system comprising a primary SRAM module and a secondary memory module with a controller that identifies error-prone addresses in the primary module and redirects access requests to the secondary module, providing redundant capacity adjusted based on the likely error rate, allowing for efficient error correction without the high overhead of conventional methods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If supply voltage is reduced to lower power consumption, then power consumption decreases, but reliability of SRAM decreases

Engineering Contradiction:
Improvepower consumptionVSAvoidreliability of SRAM
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The memory system is segmented into a primary SRAM module for normal operations and a secondary memory module for storing correction data. This segmentation allows the primary memory to operate at low voltage for power efficiency while the secondary memory handles error correction, thus resolving the contradiction between low power consumption and reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A controller acts as an intermediary between the primary and secondary memory modules. It monitors errors in the primary memory and coordinates with the secondary memory to correct them, enabling the primary memory to maintain low voltage operation while reliability is preserved through the intermediary's error management.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If conventional error correction methods are used, then reliability is improved, but storage space overhead increases significantly

Engineering Contradiction:
Improvedata storage reliabilityVSAvoidstorage space
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The error correction functionality is extracted from the primary SRAM and implemented in a separate secondary memory module. This extraction allows the primary memory to maintain full capacity for data storage while the secondary memory, with much smaller capacity, handles only the correction information, thus resolving the contradiction between reliability and storage space overhead.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of applying uniform error correction across the entire memory system, the invention applies error correction locally only to specific error-prone addresses identified in the primary memory. The controller directs access requests to the secondary memory only when errors are detected at specific locations, optimizing storage space utilization while maintaining reliability where needed.

Inventive Principle:
Principle #3Local quality

Data Source

PatentEP3379416B1Memory system
Publication Date: 2023.06.14 NXP BV
  • EP3379416B1 patent drawingFigure 1
  • EP3379416B1 patent drawingFigure 2
  • EP3379416B1 patent drawingFigure 3

AI summary

A memory system is disclosed, comprising a primary memory module (101), a secondary memory module (102), and a controller (103). The controller (103) is configured to identify addresses in the primary memory module requiring correction, and is further configured to receive a memory access request identifying an address in the primary memory module (101). The controller (103) is configured to determine whether the address is identified as requiring correction and, if it is not, to direct the memory access request to the primary memory module (101). If the address is identified as requiring correction, the controller (103) is configured to direct the memory access request to the secondary memory module (102).