Memory Error Analysis Using CRC, ECC, and Address Validation
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Solution Overview
Problem
Uncorrectable errors in storage devices, such as NAND flash memories, often result in uncorrectable ECC (UECC) failures, which can be caused by various failure mechanisms like logical to physical address corruption, physical address corruption, or reliability issues, making it difficult to determine the exact failure mechanism for appropriate mitigation.
Innovation Solution
The proposed solution involves generating a pseudo-random seed from the physical address to scramble data, CRC, and ECC values, creating a storage data unit that can be de-scrambled and analyzed for errors, using cyclic redundancy checks and error correction decoding to determine the type of error occurred, allowing for targeted mitigation actions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction codes (ECC) are used to correct errors in storage devices, then data reliability is improved, but uncorrectable errors still occur and cannot be differentiated by type
Solution Approach 1:
The patent segments the error analysis process into multiple independent checks: initial checksum verification, ECC decoding status analysis, and logical address validation. Each segment provides specific information about different failure mechanisms, allowing differentiation between address corruption, media defects, and reliability issues without compromising data reliability protection.
Solution Approach 2:
The patent introduces an intermediary analysis layer between ECC decoding and final error classification. This intermediary process uses multiple indicators (checksum match, decoder status, address validation) to mediate the translation of raw error signals into differentiated failure mechanism categories, preserving both data reliability and failure information.
2Measurement precision
If multiple error detection methods are implemented to differentiate failure mechanisms, then error type identification accuracy is improved, but system complexity increases
Solution Approach 1:
The patent divides the error detection system into three independent modular components: checksum calculation module, ECC decoding module, and logical address validation module. Each module performs a specific function and can be implemented independently, reducing overall system complexity while maintaining high error type identification accuracy through their combined results.
Solution Approach 2:
The patent creates a multi-functional error analysis system where a single error detection mechanism serves multiple purposes: detecting address corruption, identifying media defects, and determining reliability issues. This universal approach improves measurement precision without proportionally increasing device complexity by leveraging the same infrastructure for multiple diagnostic functions.
Data Source
AI summary
When stored data is retrieved from a memory using a given logical address, an initial checksum is computed over the data, and an error correction decoding can be performed to generate a decoded data payload. The decoded data payload may include decoded data and a decoded logical address. An uncorrectable error failure analysis can be performed based on the initial checksum, the error correction decoder status, and the decoded logical address to determine which error type has occurred from a plurality of error types.