Memory System Error Bit Estimation via Partial Data Transfer
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Solution Overview
Problem
Current memory systems require significant time for patrol operations due to the need to read and process large amounts of data to estimate error bits, which hampers efficiency and data retention reliability.
Innovation Solution
Implementing a memory system with a controller that calculates an FBC estimate value using reduced data transfer from NAND memory chips, employing methods like 4-point, 3-point, or 1-point read methods to estimate error bits without transferring full page data, thereby reducing data transfer and processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full page data is read and transferred from NAND memory chips to estimate error bits, then measurement precision of error bits is improved, but loss of time increases significantly
Solution Approach 1:
The patent extracts only the essential information needed for error bit estimation from the full page data. Instead of transferring complete page data, the system reads and transfers only specific portions or characteristics of the data that are sufficient to calculate the FBC estimate value, thereby reducing transfer time while maintaining estimation accuracy
Solution Approach 2:
The patent applies partial action by performing error bit estimation using a subset of the full data set. The FBC estimate value is calculated based on partial page data or sampled data points rather than processing the entire page, which reduces the time required for patrol operations while still providing reliable error bit estimates
2Loss of information
If full page data is transferred from NAND memory chips, then data completeness is improved, but device complexity and processing load increase
Solution Approach 1:
The patent extracts only the necessary data elements required for FBC estimate calculation from the full page data. The control circuit identifies and transfers only the relevant portions of data that contribute to error bit estimation, eliminating unnecessary data transfer and processing complexity
Solution Approach 2:
The system performs partial data processing by calculating the FBC estimate value using a reduced data set. This partial action approach maintains sufficient information for accurate error bit estimation while significantly reducing the processing load and complexity compared to handling complete page data
Data Source
AI summary
A memory system includes a semiconductor memory that includes a cell unit having a plurality of memory cells, and a control circuit for controlling the plurality of memory cells, and a memory controller configured to control the semiconductor memory. The control circuit is configured to execute a data read operation on the cell unit by using one or more read voltages, acquire first data by the data read operation, generate second data with a data size smaller than the first data, based on the first data, and transmit the second data to the memory controller. The memory controller is configured to determine, based on the second data, whether or not to rewrite the page data written in the cell unit.