Memory Error Check Address Generation Circuit for Defect Classification

The patent performs preliminary error check operations during the memory initialization phase before normal operation begins. This preliminary action identifies and maps defective memory cells in advance, allowing the system to proactively avoid these regions during subsequent read/write operations, thereby maintaining high reliability despite increased memory capacity.

The patent introduces an intermediary error check address generation circuit that acts as a mediator between the memory control logic and the physical memory cells. This circuit generates specialized error check addresses that systematically probe memory regions, identifies defective cells, and provides corrected address mappings to the controller, thus resolving the contradiction between capacity and reliability.

The patent implements periodic error check operations at strategically determined intervals rather than continuous checking. The error check address generation circuit systematically progresses through memory regions at controlled rates, performing checks periodically based on address increments. This periodic approach maintains high error detection capability while minimizing the time penalty by avoiding unnecessary continuous verification.

The patent employs a skipping strategy in the error check address generation where, after detecting a defective region, the address increment logic skips over problematic areas and jumps to subsequent regions. This rushing through of known-good regions reduces the overall checking time while maintaining detection precision by focusing verification efforts on boundary regions where defects are most likely to occur.

The patent implements dynamic address increment logic that adapts the step size based on the checking context. The error check address generation circuit modifies its increment behavior: using smaller steps (including 1-step increments) in regions where defects are suspected or newly encountered, and larger steps in regions already verified as good. This dynamic adjustment maintains comprehensive coverage in critical areas while accelerating checking in safe zones.

The patent changes the address increment parameter dynamically during the error check process. The error check address generation circuit modifies the address step size based on detected error patterns, previously checked regions, and confidence levels. By changing this parameter adaptively, the system achieves both thorough coverage where needed and high speed where permissible, resolving the contradiction between coverage and checking speed.