Memory Error Check and Scrub via Off-lined Region List
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Solution Overview
Problem
As memory device capacity increases, it becomes challenging to fabricate devices without defective memory cells, leading to the need for error correction methods such as redundant cells and error correction circuits, but these methods do not fully address the issue of efficiently identifying and isolating faulty regions within memory systems.
Innovation Solution
A method and system for error checking and scrubbing in memory devices, utilizing bit line sense amplifiers, error detection circuits, and memory controllers to identify and off-line regions with excessive errors, preventing further counting and operation on already identified bad regions to optimize error handling and system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error check and scrub operations are performed on all regions continuously, then error detection capability is improved, but system efficiency deteriorates due to repeated checks on already identified bad regions
Solution Approach 1:
The patent applies preliminary action by maintaining an off-lined region list that pre-identifies bad regions before error check operations are performed. The memory controller checks whether target regions exist in the off-lined region list before executing error check and scrub operations, thereby avoiding redundant operations on already identified bad regions and improving system efficiency while maintaining error detection capability for good regions
Solution Approach 2:
The patent inverts the conventional approach by instead of checking all regions and then identifying bad ones, it first identifies and records bad regions in an off-lined region list, then inverts the operation logic to skip these pre-identified bad regions. This inversion of the process sequence eliminates wasted operations while preserving comprehensive error detection for remaining good regions
2Reliability
If redundant memory cells and error correction circuits are used, then error correction capability is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the memory into multiple regions and implementing region-based error check and scrub operations. By segmenting the memory space and processing regions independently with region address management, the system can apply error correction selectively to specific regions rather than uniformly across the entire memory, thereby managing complexity through modular region handling while maintaining comprehensive error correction capability
Solution Approach 2:
The patent applies universality by creating a multi-functional memory system that can perform both normal memory operations and error check/scrub operations through the same physical memory cells and bit line sense amplifiers. The region address management mechanism enables the system to switch between different operational modes using the same hardware resources, avoiding the need for separate dedicated error correction hardware and thus controlling device complexity while maintaining versatile error correction capability
Data Source
AI summary
A method for operating a memory includes: a first region error checking operation of reading data of N memory cells from each of K, rows, where K is an integer equal to or greater than 2, by using N first bit line sense amplifiers, where N is an integer equal to or greater than 2 and checking errors; processing first region error information based on the number of errors detected in the first region error checking operation; a second region error checking operation of reading data of N memory cells in each of K rows by using N second bit line sense amplifiers and checking errors; and processing second region error information based on the number of errors detected in the second region error checking operation.