Memory Error Correction with Chip Kill and Power Saving

The patent segments the error correction problem into two distinct phases: a learning phase where the system identifies failed memory chips through syndrome analysis, and a recovery phase where the system corrects errors using discriminator expressions. This segmentation allows the system to achieve reliable error correction with less than two full redundant memory chips by treating chip failure identification and error correction as separate, manageable tasks rather than requiring complete redundancy from the outset.

The patent implements preliminary action by performing syndrome computation and chip failure identification during normal memory operations. The system proactively learns about failed chips and prepares correction mechanisms before actual data corruption occurs. This preliminary identification and preparation of correction expressions enables the system to handle errors efficiently without requiring extensive redundant storage capacity.

The patent employs periodic action by implementing error correction as a two-phase process: during normal operations, the system periodically computes syndromes and identifies failed chips in a learning phase, then transitions to a recovery phase where pre-computed discriminator expressions are used for rapid error correction. This periodic alternation between learning and recovery phases allows the system to maintain high-speed access while periodically enhancing error detection capability without requiring continuous redundant operations.

The system performs preliminary syndrome analysis and chip failure identification during normal memory operations, preparing correction expressions in advance. When errors occur, the pre-computed discriminator expressions enable rapid correction without requiring extensive real-time computation or additional redundant access cycles, thus maintaining high memory access speed while improving error detection capability.

The patent applies partial action by implementing a learning phase that progressively identifies failed chips and builds correction capability incrementally. The system uses discriminator expressions that are computed based on actual observed failures rather than assuming complete redundancy is needed. This partial approach allows the system to achieve reliable chip failure correction by addressing only the specific failures that occur, rather than allocating full redundant chips for all possible failure scenarios, thereby preserving more usable memory capacity.

The system dynamically changes parameters by transitioning between learning and recovery phases, adjusting the level of redundancy utilization based on actual failure patterns. During the learning phase, the system adapts to specific chip failures and computes appropriate discriminator expressions. This parameter change allows the system to optimize the balance between correction reliability and usable capacity by tailoring the correction mechanism to actual observed failures rather than using fixed full redundancy.