Memory Error Classification Using Cache Tag Bits and Flush Operations
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Solution Overview
Problem
Existing methods for determining the cause of memory errors in computer systems are inadequate, particularly in the presence of cache memories, as they can lead to misdiagnosis of errors due to cache interference and inability to differentiate between certain types of errors such as 'leaky cell' or 'bad reader/writer' conditions.
Innovation Solution
A system that detects correctable memory errors by reading tag bits, performing read and write operations, and using test results to determine the error cause, including flushing cache lines, clearing asynchronous fault registers, and using atomic compare-and-swap operations to accurately classify errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing error determination mechanisms are used in the presence of cache memories, then error cause determination is attempted, but misdiagnosis occurs due to cache interference
Solution Approach 1:
The patent extracts the cache memory from the error testing process by flushing cache lines before performing error determination tests. This ensures that memory accesses directly target main memory without cache interference, allowing accurate error cause determination while maintaining system reliability
Solution Approach 2:
The patent introduces a cache state tracking mechanism that monitors cache coherence protocol states as an intermediary between the error testing mechanism and main memory. This intermediary provides information about cache line states to distinguish between intermittent errors (cache-related) and persistent errors (memory-related), resolving the misdiagnosis problem
2Ease of operation
If cache lines are flushed to force main memory access for error testing, then error testing can proceed, but dirty cache lines are written back to memory which may correct the error
Solution Approach 1:
The patent performs preliminary actions by tracking cache line states and identifying dirty cache lines before flushing. This allows the system to prevent incorrect error corrections by knowing which cache lines contain modified data that should not be written back during error testing
Solution Approach 2:
The patent implements feedback through cache state tracking that provides information about cache line coherence states back to the error determination logic. This feedback mechanism enables the system to make informed decisions about whether to proceed with flushing or to handle dirty cache lines appropriately, maintaining error testing accuracy
3Device complexity
If simple retry mechanisms are used, then error handling is simple, but the system cannot differentiate between intermittent errors, persistent errors, sticky errors, leaky cell errors, or bad reader/writer errors
Solution Approach 1:
The patent segments the error determination process into distinct phases: cache state verification, error detection, error type classification, and remedial action selection. This segmentation allows the system to accurately classify different error types (intermittent, persistent, sticky, leaky cell, bad reader/writer) while maintaining manageable complexity through structured processing
Solution Approach 2:
The patent changes the parameter being measured from simple error detection to comprehensive error characterization by incorporating cache state information, access pattern analysis, and multiple test operations. This parameter change enables precise error classification while the structured approach keeps the overall system complexity manageable
Data Source
AI summary
One embodiment of the present invention provides a system that determines the cause of a correctable memory error. First, the system detects a correctable error during an access to a memory location in a main memory by a first processor, wherein the correctable error is detected by error detection and correction circuitry. Next, the system reads tag bits for a cache line associated with the memory location, wherein the tag bits contain address information for the cache line, as well as state information indicating a coherency protocol state for the cache line. The system then tests the memory location by causing the first processor to perform read and write operations to the memory location to produce test results. Finally, the system uses the test results and the tag bits to determine the cause of the correctable error, if possible.