Memory Error Coalescing with Crossbar Routing for Bad Bits
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Solution Overview
Problem
The presence of random bit errors in memories negatively impacts the robustness and availability of computer systems, as existing technologies struggle to effectively manage and correct these errors.
Innovation Solution
A programmable crossbar matrix or array of steering multiplexors is used to coalesce data from multiple 'bad' bit positions within symbols of a codeword into a single check symbol, improving error detection and correction by concentrating unreliability into a single symbol.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data from multiple bad bit positions is coalesced into a single check symbol, then error detection and correction capability is improved, but device complexity increases
Solution Approach 1:
The patent segments the codeword into data symbols and check symbols, and further segments bad bit positions into groups that can be coalesced into single check symbols. This segmentation allows systematic error coalescing while managing complexity through structured organization of bits and symbols.
Solution Approach 2:
The patent introduces check symbols as intermediary elements that receive coalesced data from multiple bad bit positions. These check symbols act as mediators between the unreliable data bits and the error correction mechanism, concentrating errors into manageable units that can be detected and corrected more effectively.
2Reliability
If error coalescing is implemented across multiple memory ranks, then robustness against random bit errors is improved, but switching complexity and power consumption increase
Solution Approach 1:
The patent creates a universal error coalescing mechanism that can operate across multiple memory ranks using the same crossbar matrix structure. The switching network is designed to handle coalescing operations for any rank, making the system multi-functional and reducing the need for separate error correction hardware for each rank.
Solution Approach 2:
The patent extends error coalescing from a single-rank operation to multi-rank operation by adding the rank dimension to the coalescing process. Instead of handling errors in isolation within one rank, the system coalesces errors across multiple ranks simultaneously, utilizing the additional dimensional space to improve overall system robustness.
3Reliability
If bad bit positions are identified and coalesced during initialization, then error management effectiveness is improved, but initialization time and loss of time increase
Solution Approach 1:
The patent performs error coalescing configuration during initialization or boot time, which is a preliminary action taken before normal operation. By identifying bad bit positions and configuring the crossbar matrix in advance, the system prepares error correction capabilities beforehand, so that during normal operation, error coalescing occurs automatically without additional time loss.
Solution Approach 2:
The system performs self-diagnosis during initialization to identify bad bit positions in the memory ranks. This self-service approach allows the memory system to automatically characterize its own errors and configure the error coalescing mechanism without external intervention, improving error management effectiveness while minimizing the time required for setup.
Data Source
AI summary
A programmable crossbar matrix or an array of steering multiplexors (MUXs) coalesces (i.e., routes) the data values from multiple known “bad” bit positions within multiple symbols of a codeword, to bit positions within a single codeword symbol. The single codeword symbol receiving the known “bad” bit positions may correspond to a check symbol (vs. a data symbol). Configuration of the routing logic may occur at boot or initialization time. The configuration of the routing logic may be based upon error mapping information retrieved from system non-volatile memory (e.g., memory module serial presence detect information), or from memory tests performed during initialization. The configuration of the routing logic may be changed on a per-rank basis.