Memory Error Coalescing via Crossbar Routing for ECC Symbols
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Solution Overview
Problem
Random bit errors in memories negatively impact the robustness and availability of computer systems, as existing technologies fail to effectively manage and correct these errors across multiple bit positions within a codeword.
Innovation Solution
A programmable crossbar matrix or array of steering multiplexors coalesces data from multiple 'bad' bit positions into a single codeword symbol, utilizing error mapping information to configure the routing logic at boot or initialization time, thereby improving error detection and correction by concentrating unreliability into a single symbol.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data from multiple bad bit positions is coalesced into a single codeword symbol, then error detection and correction capability is improved, but device complexity increases due to programmable crossbar matrix or steering multiplexor routing logic
Solution Approach 1:
The patent segments the codeword into multiple symbols and identifies specific bad bit positions within each symbol. The routing logic is segmented into configurable paths that can be programmed to route data from identified bad bit positions to designated target positions, allowing modular error management rather than requiring complete reconfiguration of the entire data path.
Solution Approach 2:
The patent performs preliminary identification of bad bit positions during initialization or boot time, before normal operation begins. The routing logic is pre-configured with error mapping information that maps bad bit positions to target positions, so that during normal operation the coalescing function can be executed directly without real-time analysis, reducing operational complexity.
2Reliability
If error mapping information is used to configure routing logic at boot time, then error coalescing effectiveness is improved, but loss of time occurs during initialization
Solution Approach 1:
The patent performs error mapping and routing configuration as a preliminary action during boot or initialization time. Bad bit positions are identified and mapped to target positions in advance, and the routing logic is programmed with this mapping information before normal operation begins. This one-time initialization overhead enables efficient error coalescing during subsequent operations without repeated configuration delays.
Solution Approach 2:
The system performs self-diagnosis during initialization to identify bad bit positions in its own memory structures. The error mapping information is generated autonomously by the system itself through internal testing and analysis, eliminating the need for external characterization or manual configuration, thereby reducing overall initialization time while maintaining effectiveness.
3Reliability
If multiple bad bit positions are consolidated into a single symbol, then robustness against random bit errors is improved, but manufacturing precision requirements increase for the routing logic
Solution Approach 1:
The patent segments the routing function into discrete configurable paths within the crossbar matrix or steering multiplexors. Each path can be independently programmed to route data from a specific bad bit position to a target position. This segmentation allows standard manufacturing processes to produce the routing logic with typical precision, while the programmable nature enables precise error correction functionality to be achieved through configuration rather than requiring ultra-precise manufacturing.
Solution Approach 2:
The patent uses programmable routing logic where the behavior is determined by configuration parameters (error mapping information) rather than fixed physical connections. By changing the logical parameters through programming, the system achieves precise error coalescing functionality without requiring corresponding physical manufacturing precision. The same physical hardware can be reconfigured for different error patterns.
Data Source
AI summary
A programmable crossbar matrix or an array of steering multiplexors (MUXs) coalesces (i.e., routes) the data values from multiple known “bad” bit positions within multiple symbols of a codeword, to bit positions within a single codeword symbol. The single codeword symbol receiving the known “bad” bit positions may correspond to a check symbol (vs. a data symbol). Configuration of the routing logic may occur at boot or initialization time. The configuration of the routing logic may be based upon error mapping information retrieved from system non-volatile memory (e.g., memory module serial presence detect information), or from memory tests performed during initialization. The configuration of the routing logic may be changed on a per-rank basis.