Memory Control Circuit Error-Code Merging for Combined Data Writes

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Solution Overview

Problem

In the process of combining sub-data in rewritable non-volatile memory modules, error bits can be generated due to cosmic rays or other unpredictable factors, making it challenging to efficiently generate error detecting codes for the combined data.

Innovation Solution

A data writing method that involves receiving and generating error detecting codes for each sub-data, combining these codes to check for errors in the combined data, and storing the combined data and error detecting code into the non-volatile memory module without the need to read the sub-data into a buffer memory, thereby preventing error bits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If sub-data is read into buffer memory to generate error detecting codes for combined data, then error detection capability is maintained, but error bits may be introduced during the read-write process and system complexity increases

Engineering Contradiction:
Improveerror detection capabilityVSAvoiderror bits introduced during read-write
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent extracts the error detection function from the data itself by generating separate error detecting codes for each sub-data. These codes are combined to form a composite error detecting code that can verify the integrity of combined data without requiring the data to be read back into buffer memory, thereby eliminating the source of potential error bits.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies preliminary error detection by generating error detecting codes for each sub-data immediately when the sub-data is written into the non-volatile memory module. This preliminary error detection mechanism is established before any potential read-write operations that could introduce errors, allowing error-free verification of combined data.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If sub-data is read into buffer memory to combine and generate error detecting codes, then combined data can be verified, but writing efficiency decreases due to additional read-write operations

Engineering Contradiction:
Improvedata integrity verificationVSAvoidwriting efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent performs preliminary error detection code generation for each sub-data at the time of writing. This eliminates the need for subsequent read operations into buffer memory to generate error detecting codes for combined data, thereby maintaining writing efficiency while ensuring data integrity verification.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent merges the error detecting codes of multiple sub-data to generate a composite error detecting code for the combined data. This merging process occurs directly in the memory module without requiring external buffer memory access, thus maintaining writing efficiency while achieving comprehensive error detection for the combined data.

Inventive Principle:
Principle #5Merging (Combining)

3Measurement precision

If error detecting codes are generated for each sub-data and combined, then error detection accuracy improves, but processing complexity increases

Engineering Contradiction:
Improveerror detection accuracyVSAvoidprocessing complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the error detection process by generating separate error detecting codes for each sub-data. This segmentation allows independent verification of each sub-data's integrity while maintaining overall system manageability. The segmented approach improves detection accuracy without overwhelming processing complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent combines the segmented error detecting codes through a systematic merging process to generate a composite error detecting code. This merging operation is designed to be computationally efficient, achieving high error detection accuracy while controlling processing complexity through structured code combination algorithms.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10983858B2Data writing method, memory control circuit unit and memory storage device
Publication Date: 2021.04.20 PHISON ELECTRONICS
  • US10983858B2 patent drawing
  • US10983858B2 patent drawing
  • US10983858B2 patent drawing

AI summary

A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: receiving a first sub-data of a plurality of sub-data of a first data and generating a first error detecting code corresponding to the first sub-data; receiving a second sub-data of the plurality of sub-data of the first data and generating a second error detecting code corresponding to the second sub-data; combining the first error detecting code and the second error detecting code to obtain a third error detecting code, wherein the third error detecting code is used to check whether a second data formed by combining the first sub-data and the second sub-data has an error; and storing the second data and the third error detecting code into a rewritable non-volatile memory module.