Memory Error-Coding Architecture for Controller and Address Integrity
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Solution Overview
Problem
Modern memory systems face challenges in detecting and correcting errors not only in memory cells but also in memory controllers, due to increasing complexity, leading to a demand for improved error detection and correction techniques.
Innovation Solution
A memory system is designed with multiple error detection circuits that generate and utilize error detection codes (CRC, CRC-10, and RS) to cover data and addresses during write and read operations, enabling efficient error detection and correction across both memory and controller components, preventing capacity waste by not storing addresses in memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple error detection circuits and codes are used to detect and correct errors in both memory and controller, then error detection and correction capability is improved, but device complexity increases
Solution Approach 1:
The error detection and correction function is segmented into multiple specialized circuits: a first error detection circuit for generating initial error detection codes, a second error detection circuit for generating additional error detection codes, and a third error detection circuit for generating final error detection codes. Each circuit operates on different data segments (host data, system data, meta data) to provide comprehensive error protection while maintaining modular architecture that manages complexity.
Solution Approach 2:
The patent implements nested error detection where error detection codes are embedded within the data structure itself. The first error detection codes are generated from host data, then second error detection codes are generated from system data that includes the first error detection codes, and finally third error detection codes are generated from complete system data including all previous codes. This nested structure allows multiple layers of error protection without requiring separate independent systems.
2Reliability
If error detection codes are generated and stored for all data including addresses, then error detection coverage is improved, but memory capacity is wasted
Solution Approach 1:
The patent extracts the address information from the error detection process by using only the data portion for generating error detection codes that need to be stored. The first error detection circuit generates codes from host data only, and subsequent circuits generate codes from system data that excludes the address portion. This extraction of address information from the storage requirement maintains error detection coverage for data integrity while preventing waste of memory capacity on address storage.
Solution Approach 2:
The patent introduces meta data as an intermediary structure that contains the error detection codes. Instead of storing error detection codes directly alongside all data including addresses, the meta data serves as a mediator that organizes and stores the codes efficiently. The meta data includes the first, second, and third error detection codes along with their corresponding data, creating a structured intermediate layer that optimizes storage usage while maintaining comprehensive error detection capability.
Data Source
AI summary
A memory system includes: a first error detection circuit suitable for generating a first error detection code using host data and a host address which are transferred from a host; a second error detection circuit suitable for generating a second error detection code using system data including one or more host data, a logical address corresponding to one or more host addresses, a physical address corresponding to the logical address and one or more first error detection codes; a third error detection code suitable for generating a third error detection code using the system data, the one or more first error detection codes and the second error detection code; and a first memory suitable for storing the system data, the one or more first error detection codes, the second error detection code and the third error detection code.