Semiconductor Memory Error Control Circuit for Coupling Noise

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Semiconductor memory apparatuses experience erroneous operations due to glitches in auto-precharge bank selection signals caused by coupling noise, leading to abnormal voltage level reductions in unselected banks, resulting in incorrect auto-precharge signal generation.

Innovation Solution

Incorporating an error control unit that supplies an external voltage to the first node when an activated internal command is applied, preventing erroneous voltage level reductions in unselected banks, and a signal generation unit that generates bank operation signals based on the voltage level of the first node, ensuring only selected banks perform predetermined operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If coupling noise is present in the auto-precharge bank selection signal, then the voltage level of unselected banks is erroneously reduced, but this leads to incorrect auto-precharge signal generation and erroneous operations

Engineering Contradiction:
Improveoperation accuracyVSAvoidcoupling noise
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces a mask signal as an intermediary element that mediates between the noisy auto-precharge bank selection signal and the voltage control mechanism. The mask signal is generated by ANDing the auto-precharge bank selection signal with another signal, and this mask signal controls whether the voltage level reduction actually occurs. This intermediary layer filters out erroneous signals caused by coupling noise while allowing valid signals to pass through, thus resolving the contradiction between operational reliability and noise susceptibility.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the voltage level of the first node is reduced to generate an activated bank operation signal, then the selected bank performs the predetermined operation, but unselected banks may experience abnormal voltage reductions due to noise

Engineering Contradiction:
Improveoperation speedVSAvoidsignal accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by generating the mask signal before the voltage level reduction occurs. The mask signal is prepared in advance by combining the auto-precharge bank selection signal with another signal through an AND operation. This preliminary preparation ensures that when the voltage level reduction is executed, it only affects the intended selected bank and not unselected banks, thus maintaining both operational speed and signal accuracy.

Inventive Principle:
Principle #10Preliminary action

3Extent of automation

If the bank control unit reduces the voltage level of the first node in response to the auto-precharge command and bank selection signal, then the auto-precharge operation is executed, but coupling noise causes erroneous voltage reductions in unselected banks

Engineering Contradiction:
Improveauto-precharge functionVSAvoidcoupling noise interference
Core Design Contradiction:
Extent of automationVSObject-affected harmful factors

Solution Approach 1:

The mask signal serves as an intermediary that protects the automatic precharge function from coupling noise interference. By ANDing the auto-precharge bank selection signal with another signal to generate the mask signal, the system ensures that the automatic voltage level reduction only occurs for the correctly selected bank. This intermediary mechanism maintains the automation of the precharge function while filtering out noise-induced erroneous operations in unselected banks.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8730748B2Semiconductor memory apparatus equipped with an error control circuit for preventing coupling noise
Publication Date: 2014.05.20 SK HYNIX INC
  • US8730748B2 patent drawing
  • US8730748B2 patent drawing
  • US8730748B2 patent drawing

AI summary

A semiconductor memory apparatus includes a plurality of memory banks, wherein each memory bank includes a bank control unit configured to reduce a voltage level of a first node to a ground voltage level when the memory bank is selected to perform a predetermined operation; an error control unit configured to supply an external voltage to the first node when the memory bank is not selected to perform the predetermined operation; and a signal generation unit configured to generate a bank operation signal in response to the voltage level of the first node.