Memory Device Error Control Coding and Data Masking Circuitry
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Solution Overview
Problem
Current memory devices face challenges in maximizing system performance, reducing power consumption, and enhancing reliability due to inefficiencies in memory control functions, self-refresh modes, and temperature-controlled refresh operations, which impact mean-time-between-failure (MTBF) and overall system design.
Innovation Solution
The development of a memory device with error control coding, data masking circuitry, programmable preamble control, self-refresh circuitry, and temperature-controlled refresh mechanisms, including a MEMcal command for periodic DLL updates, allows for improved data integrity, reduced power consumption, and adaptive refresh rates based on environmental conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If continuous DLL synchronization is performed, then data integrity is maintained, but power consumption increases
Solution Approach 1:
The patent implements periodic DLL synchronization instead of continuous synchronization. The DLL is synchronized at specific intervals determined by a synchronization counter, which increments with each command and resets when reaching a threshold value. This periodic approach maintains data integrity while significantly reducing power consumption compared to continuous synchronization.
Solution Approach 2:
The patent employs feedback mechanisms through error control coding circuitry that monitors data integrity and provides feedback to the controller. When errors are detected, the system can adjust synchronization timing or retry operations, optimizing the balance between maintaining reliability and reducing power consumption.
2Use of energy by moving object
If self-refresh mode is used to reduce power consumption, then power usage decreases, but exit time from refresh mode increases
Solution Approach 1:
The patent implements preliminary actions by updating programmable settings during self-refresh mode before the device needs to exit refresh mode. The controller can prepare for upcoming operations by programming preamble lengths, timing parameters, or other configuration values while in the low-power refresh state, so that when exit is needed, the device is already optimized for rapid transition without requiring lengthy reconfiguration periods.
3Reliability
If error control coding is implemented, then data integrity is improved, but device complexity increases
Solution Approach 1:
The patent extracts and implements error control coding functionality as a dedicated circuit module within the memory device. By separating the error detection and correction logic from the main data path, the system achieves improved data integrity through mechanisms such as parity checking or checksum validation, while managing complexity through modular design where the error control circuitry can be independently configured and optimized.
4Device complexity
If fixed preamble time is used for data transfer, then timing is simplified, but performance cannot be optimized for varying conditions
Solution Approach 1:
The patent implements dynamic preamble time control where the controller can adjust the preamble length based on operating conditions such as data rate, temperature, or signal quality. The programmable preamble control circuitry allows the system to optimize timing parameters for varying performance requirements, enabling faster data transfer when conditions permit while maintaining reliability when signal stability is compromised, all without significantly increasing timing control complexity.
Data Source
AI summary
An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.