Dynamic Error Control Prioritization in Memory Sub-systems

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Solution Overview

Problem

Conventional memory sub-systems experience delays and increased read latency due to inefficiencies in error control operations, where previously successful error control operations may not consistently remedy subsequent read operation failures, leading to delays in executing alternative operations.

Innovation Solution

Implementing a dynamic prioritization of error control operations, where successful error control operations are identified and reordered for immediate execution, with less successful operations being removed or repositioned based on success metrics and latency, ensuring that the most effective operations are executed first.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If conventional error control operations are executed in a fixed order, then the system maintains simplicity in operation management, but read latency increases due to inefficiencies in error remediation

Engineering Contradiction:
Improveread latencyVSAvoiderror control operation management
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent implements dynamic prioritization of error control operations by maintaining a data structure that tracks success metrics for each operation and automatically reorders them based on performance. The system dynamically adjusts the execution order of error control operations rather than using a fixed sequence, allowing the most successful operations to be attempted first, thereby reducing read latency while adapting to changing error patterns in the memory sub-system.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system incorporates feedback mechanisms by monitoring the success or failure of each error control operation and using this information to adjust the prioritization order. The data structure records outcomes of previous operations, and this feedback is used to reorder operations for subsequent execution, creating a closed-loop system that continuously optimizes error remediation efficiency based on actual performance data.

Inventive Principle:
Principle #23Feedback

2Reliability

If all error control operations are attempted in sequence, then comprehensive error coverage is achieved, but processing time and read latency increase

Engineering Contradiction:
Improveerror remediation success rateVSAvoidread operation throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by pre-sorting and prioritizing error control operations based on their historical success metrics before they are needed. The system maintains a pre-computed ordered list of operations in the data structure, so when an error occurs, the most likely successful operations are already positioned for immediate execution, eliminating the need to attempt all operations in sequence and thereby improving both reliability and productivity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system changes the parameter of operation execution order based on success metrics. Rather than executing operations in a static sequence, the patent dynamically adjusts the order parameter according to measured performance data, prioritizing operations with higher success rates. This parameter change enables the system to achieve comprehensive error coverage while minimizing processing time by focusing on the most effective operations first.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If error control operations with lower success metrics are executed first, then all operations are given equal opportunity, but overall error remediation efficiency decreases

Engineering Contradiction:
Improveerror remediation efficiencyVSAvoidoperation selection flexibility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamics by making the operation selection process adaptive rather than static. The data structure dynamically reorders operations based on updated success metrics, allowing the system to prioritize high-performing operations while maintaining the ability to adapt when error patterns change. This dynamic approach improves error remediation efficiency without permanently sacrificing flexibility, as the system can still attempt lower-priority operations if higher-priority ones fail.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the prioritization parameter of error control operations based on measured success metrics. Operations are reordered according to their performance data, with higher-success operations positioned for earlier execution. This parameter change optimizes error remediation efficiency by focusing computational resources on the most effective operations first, while the system retains adaptability to adjust priorities as new performance data becomes available.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11740957B2Prioritization of error control operations at a memory sub-system
Publication Date: 2023.08.29 MICRON TECHNOLOGY INC
  • US11740957B2 patent drawing
  • US11740957B2 patent drawing
  • US11740957B2 patent drawing

AI summary

A failure of a first memory access operation is detected at a memory device. Responsive to the detection, a first error control operation and a second error control operation are performed. In response to a determination that the second error control operation has remedied the failed first memory access operation, the second error control operation is associated with a second priority which is higher than a first priority associated with the first error control operation.