Memory System Error Correction for Long-Term Data Integrity
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Solution Overview
Problem
Existing memory systems face challenges in ensuring data reliability due to bit errors that can occur when memory cells are left for a long time after the first write operation, leading to potential data corruption.
Innovation Solution
The memory system employs a controller that executes a first write operation and a second write operation, with a first circuit checking for bit errors. If an error is detected, the second write operation corrects the bit error by writing data that includes a third bit obtained from error correction, ensuring accurate data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If the memory cell is left for a long time after the first write operation, then the data storage capacity is maintained, but bit errors occur leading to data corruption
Solution Approach 1:
The patent performs a preliminary check for bit errors using a first circuit before the second write operation. If errors are detected, the system corrects them in advance by writing corrected data (including a third bit from error correction) during the second write operation. This preliminary error detection and correction prevents data corruption that would otherwise occur after prolonged storage.
Solution Approach 2:
The patent implements a feedback mechanism where the first circuit continuously monitors the data stored in the memory cell for bit errors. Based on the feedback from this error detection, the controller decides whether to execute the second write operation with corrected data. This closed-loop feedback ensures data integrity by responding to actual error conditions rather than relying solely on time-based intervals.
2Reliability
If the second write operation is executed to correct bit errors, then data reliability is improved, but the operation time and complexity increase
Solution Approach 1:
The patent applies partial action by executing the second write operation only when necessary - specifically, only when the first circuit detects bit errors in the data read from the memory cell. Instead of performing the correction write operation unconditionally or at fixed time intervals, the system performs it selectively based on actual error conditions, thereby reducing unnecessary operation time while maintaining data reliability.
Solution Approach 2:
The error detection by the first circuit is performed preliminarily before the second write operation. This preliminary check allows the system to prepare for correction only when needed, avoiding the time penalty of unconditional repeated write operations while ensuring that corrections are made in advance before data corruption occurs.
3Reliability
If error correction is performed by writing corrected data, then bit errors are reduced, but the number of write operations increases
Solution Approach 1:
The system performs error correction writing partially - only for the specific data that requires correction. The first circuit identifies which data has bit errors, and the second write operation is executed only for those specific memory cells. This selective approach maintains data accuracy while minimizing the impact on write operation efficiency by avoiding unnecessary writes to error-free data.
Data Source
AI summary
According to one embodiment, a memory system includes a semiconductor memory, a controller, and a first circuit. The semiconductor memory includes a nonvolatile memory cell. The controller is configured to cause the semiconductor memory to execute first and second write operations. The first write operation writes a first bit into the memory cell. The second write operation writes first data based on the first bit and a second bit into the memory cell. The first circuit checks whether or not the first bit includes a bit error. The controller is configured to cause the semiconductor memory to execute, in the second write operation, writing of the first data including the second bit and a third bit obtained by correcting the bit error of the first bit, in a case that the first bit includes the bit error.