Memory Error Correction via Region Erasure Tracking
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Solution Overview
Problem
Existing memory devices face challenges in effectively correcting errors, especially when errors accumulate in a single chip, as traditional error correction codes (ECC) are overwhelmed, and increasing resilience without adding more chips or reducing symbol size is difficult.
Innovation Solution
The apparatus and method introduce an error tracking circuitry that identifies and marks a memory region as an 'erasure memory region' when an error threshold is reached, allowing all read symbols from that region to be treated as erroneous, thereby extending the error correction capability beyond the initial ECC limit, enabling correction of up to twice the number of errors within that region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECC schemes are used to correct errors in memory devices, then random symbol errors can be corrected, but errors accumulating in a single memory region cannot be corrected when exceeding m/2 errors
Solution Approach 1:
The patent divides the memory device into multiple memory regions and tracks errors separately for each region. This segmentation allows the system to identify when errors are concentrated in a specific region versus randomly distributed, enabling different correction strategies for each scenario and overcoming the limitation of traditional ECC that treats all errors uniformly.
Solution Approach 2:
The patent implements preliminary error tracking for each memory region before the error correction process. By monitoring and counting errors in each region in advance, the system can determine whether errors are concentrated or random, and prepare appropriate correction strategies beforehand, allowing correction of up to m errors per region rather than being limited to m/2 total random errors.
2Reliability
If more chips are added to increase ECC symbols, then error correction capability improves, but device complexity and cost increase
Solution Approach 1:
The patent changes the parameter of error correction from treating all errors as random to treating errors as region-specific. By introducing memory region identification and separate error counting per region, the system can correct up to m errors in a single region (double the traditional capability) using the same number of ECC symbols, effectively doubling the correction capability for concentrated errors without adding more chips.
3Reliability
If symbol size is reduced to increase ECC symbols, then error correction capability improves, but coding flexibility and performance are restricted
Solution Approach 1:
The patent segments the error correction approach by memory region, allowing each region to be treated independently. This enables the system to maintain larger symbol sizes for better coding flexibility while still achieving enhanced error correction capability by tracking and correcting errors on a per-region basis, rather than being forced to reduce symbol size to increase the number of ECC symbols.
Data Source
AI summary
An apparatus and method for correcting errors in data accessed from a memory device. A plurality of read symbols are read from a memory device. Syndrome information is then determined from the n data symbols and associated m error correction code symbols. Error correction circuitry uses the syndrome information in order to attempt to locate each read symbol containing an error and to correct the errors in each of those located read symbols. Error tracking circuitry tracks which memory regions the located read symbols containing an error originate from, and, on detecting an error threshold condition, sets at least one memory region as an erasure memory region. The correction circuitry treats each read symbol as a located read symbol containing an error, such that the read symbols to be located are not all randomly distributed and more than PMAX read symbols containing errors can be corrected.