Embedded Memory Error Correction Without Processor Exceptions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing error correction circuitry in integrated circuits (ICs) fails to efficiently correct errors in embedded memory, leading to disruptions in processor operation and reduced reliability due to the need for context saving and exception handling, which adversely affects performance.
Innovation Solution
Incorporating error correction circuitry that detects and corrects correctable errors in ICs, allowing asynchronous write commands to overwrite corrupted data/instructions without invoking processor exceptions, thereby maintaining program flow and minimizing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction circuitry detects and corrects errors in embedded memory, then reliability is improved, but processor operation is disrupted due to context saving and exception handling
Solution Approach 1:
The patent extracts the error correction function from the processor's main execution flow by implementing a dedicated error correction circuit that operates independently. The circuit includes an error correction unit that detects and corrects memory errors without invoking processor exceptions, thereby separating the error correction function from the processor operation and eliminating the associated overhead of context saving and exception handling.
Solution Approach 2:
The patent introduces an intermediary error correction circuit between the memory and the processor. This circuit includes an error correction unit that acts as a mediator, intercepting memory access operations, correcting errors in advance, and presenting corrected data to the processor without requiring processor intervention. This intermediary structure prevents errors from reaching the processor, thereby maintaining processor operation efficiency while ensuring reliability.
2Reliability
If processor exceptions are invoked for error correction, then errors are corrected, but latency increases due to context saving and restoration
Solution Approach 1:
The patent implements preliminary error correction by detecting and correcting memory errors before they reach the processor. The error correction unit operates in advance during memory access operations, correcting errors in the data or instructions before they are fetched by the processor. This preliminary action eliminates the need for subsequent exception handling and context restoration, thereby reducing latency while maintaining reliability.
3Reliability
If error correction is implemented in embedded memory, then data integrity is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal error correction circuit that can handle multiple types of memory access operations (reads, writes, fills) through a single integrated structure. The error correction unit is designed to work with various memory configurations and access patterns, providing multi-functional error correction capability without requiring separate circuits for different operations. This universality reduces overall device complexity while maintaining data integrity across all memory operations.
Data Source
AI summary
An electronic system includes a processor circuit, a memory circuit, and an error correction circuit. The error correction circuit receives information read from the memory circuit. The error correction circuit detects if the information contains an error. The error correction circuit corrects the error in the information to generate corrected information and provides the corrected information and an error signal to the processor circuit. The processor circuit provides the corrected information and a write command to the memory circuit based on the error signal indicating the error. The memory circuit overwrites the information stored in the memory circuit with the corrected information in response to the write command.