Memory Error Correction Circuit for High-BER Multi-Bit Reads
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Solution Overview
Problem
As process scaling continues, bit error rates (BER) in semiconductor memory devices like DRAM increase, leading to higher chip size overhead and instability in data reliability, making it difficult to ensure stable operation.
Innovation Solution
Incorporating an error correction circuit in semiconductor memory devices to correct errors, particularly multi-bit errors, and implementing a data storage circuit to temporarily store data for correction, thereby reducing the need for additional resources and minimizing performance degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If repair cells are increased to provide data reliability in response to increased BER, then data reliability is improved, but chip size overhead increases
Solution Approach 1:
The patent segments the error correction process by dividing data into multiple chunks and correcting errors in each chunk separately. This allows the system to handle high BER scenarios without requiring a proportional increase in repair cells, as the correction is distributed across multiple smaller operations rather than requiring all errors to be corrected simultaneously by a large pool of repair cells.
Solution Approach 2:
The patent performs preliminary error correction by correcting errors in data chunks before final data assembly. This preliminary action reduces the burden on repair cells during the main data recovery process, allowing reliable operation at high BER without significantly increasing the repair cell pool size.
2Reliability
If resources are increased to correct multi-bit errors, then error correction capability is improved, but device complexity increases
Solution Approach 1:
The patent divides data into multiple chunks and applies error correction to each chunk independently. This segmentation allows the use of simpler correction circuits for each chunk rather than requiring complex circuits capable of handling all possible error patterns in the entire data set simultaneously, thus improving multi-bit error correction capability while controlling device complexity.
Solution Approach 2:
The patent corrects errors in partial data chunks rather than attempting to correct all errors in the complete data set at once. This partial action approach enables the use of less complex correction resources while still achieving reliable error correction for the overall data through iterative processing of multiple chunks.
3Reliability
If error correction processing is performed for multi-bit errors, then data reliability is improved, but timing overhead increases
Solution Approach 1:
The patent segments data into multiple chunks and performs error correction on each chunk separately and in parallel where possible. This segmentation reduces the timing overhead compared to sequential processing of the entire data set, as multiple correction operations can be initiated concurrently, thereby improving data reliability while minimizing the total time penalty for multi-bit error correction.
4Reliability
If repair cells are increased to handle high BER, then stability at high BER is improved, but manufacturing cost increases
Solution Approach 1:
The patent uses segmentation to process data in chunks, which allows stable operation at high BER using a fixed, moderate number of repair cells. This approach avoids the need to increase repair cell count proportionally with BER, thereby maintaining stability at high BER while controlling manufacturing cost by using a reasonable fixed resource allocation.
Data Source
AI summary
A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.