Integrated Memory System Error Correction Latency
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Solution Overview
Problem
Existing memory systems face high latency and resource overhead in error correction due to the need for the controller to read and process entire pages of data and parity bits, which limits performance and increases transmission bandwidth usage.
Innovation Solution
The memory system splits error correction processes between the memory and controller, allowing syndrome calculation and single-error correction in the memory, with double-error correction handled by the controller, thereby reducing latency and resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the controller reads and processes entire pages of data and parity bits for error correction, then error correction capability is improved, but latency increases and transmission bandwidth usage increases
Solution Approach 1:
The patent segments the error correction process into two parts: syndrome calculation performed in the memory device itself, and full error correction performed in the controller. This segmentation allows the memory device to prepare correction information locally without requiring the controller to read and process entire pages of data, thereby reducing latency and transmission bandwidth usage while maintaining error correction capability.
2Reliability
If the controller reads and processes entire pages of data and parity bits for error correction, then error correction capability is improved, but resource overhead in the controller increases
Solution Approach 1:
The patent extracts the syndrome calculation function from the controller and places it in the memory device. This extraction reduces the computational burden and resource overhead in the controller, as it no longer needs to perform syndrome calculation on entire pages of data. The controller only needs to handle the final error correction step, simplifying its resource requirements while maintaining full error correction capability.
3Loss of time
If syndrome calculation is performed in the memory device, then latency is reduced and transmission bandwidth usage is reduced, but the memory device complexity increases
Solution Approach 1:
The patent implements preliminary action by having the memory device perform syndrome calculation in advance, during the normal read operation, before the controller needs the data. This preliminary calculation of syndrome information allows the controller to receive pre-processed correction data, reducing latency and transmission bandwidth usage. The memory device complexity increase is acceptable because the syndrome calculation uses the existing parity bits and does not require additional hardware resources.
Data Source
AI summary
An embodiment of the present invention relates to an integrated memory system comprising at least a non-volatile memory and an automatic storage error corrector, and wherein the memory is connected to a controller by means of an interface bus. Advantageously, the system comprises in the memory circuit means, functionally independent, each being responsible for the correction of a predetermined storage error; at least one of said means generating a signal to ask a correction being external to the memory.