Semiconductor Memory Error Correction Circuit
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Solution Overview
Problem
As semiconductor memory devices undergo finer processes to increase storage capacity, the bit error ratio increases, necessitating effective error correction methods to maintain data reliability.
Innovation Solution
A semiconductor memory device and memory system that execute error correction operations by generating an error correction command and selection address, correcting errors using an error flag, and processing error information to selectively execute error correction operations based on control signals from a memory controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a finer process is applied to increase storage capacity, then storage capacity is improved, but bit error ratio increases
Solution Approach 1:
The patent segments the error correction process into multiple stages: initial error correction operation, pattern detection, and targeted re-correction operations. This segmentation allows the system to handle different error types differently, improving overall reliability without sacrificing storage capacity.
Solution Approach 2:
The patent performs preliminary error correction operations before final data retrieval, and additionally identifies error patterns to perform targeted re-correction. This preliminary action ensures that errors are corrected proactively, maintaining data reliability even as storage capacity increases through finer processes.
2Reliability
If error correction operations are performed on all data, then data reliability is improved, but processing time increases
Solution Approach 1:
The patent applies local quality by differentiating between general error correction and targeted re-correction based on detected error patterns. Instead of uniformly processing all data with the same correction intensity, the system identifies specific addresses with problematic error patterns and applies additional correction operations only to those locations, reducing overall processing time while maintaining reliability.
Solution Approach 2:
The patent implements partial action by performing error correction selectively based on detected patterns. Rather than applying excessive correction to all data uniformly, the system applies additional re-correction operations only to addresses exhibiting specific error patterns, optimizing the balance between reliability improvement and processing time consumption.
3Reliability
If multiple error correction operations are executed, then error correction capability is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service through automatic error pattern detection and automatic generation of re-correction commands. The system monitors its own error correction operations, identifies patterns indicating potential failures, and autonomously initiates targeted re-correction without external intervention. This self-service approach improves error correction capability while managing device complexity through automation rather than manual configuration.
Data Source
AI summary
A semiconductor memory device includes a command address control circuit configured to generate an error correction command and selection address for executing an error correction operation by receiving an external control signal, an error flag generation circuit configured to correct an error of data corresponding to the selection address and configured to generate a target error flag based on a pattern of the error of the data, and an error information processing circuit configured to generate a target address that is used as the selection address based on the target error flag in a target error correction operation that is executed based on the error correction operation.