Memory Error Correction via Independent Refresh and ECC Cycles
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Solution Overview
Problem
Memory devices, such as DRAM, face challenges in correcting single-bit errors before they become uncorrectable double-bit errors due to infrequent access of certain memory regions, leading to increased latency and power consumption during periodic error correction operations.
Innovation Solution
Implementing a refresh operation with error correction (REF_wECC) that independently manages cycles associated with refresh and error correction, using an ECC patrol block with error correction counters to periodically correct errors in all memory regions without disrupting normal operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If periodic error correction operations are performed on all memory regions, then reliability is improved, but latency and power consumption increase
Solution Approach 1:
The patent applies different error correction strategies to different memory regions based on their access patterns. Frequently accessed memory regions use standard error correction, while infrequently accessed regions use enhanced periodic error correction. This local differentiation resolves the contradiction by applying error correction resources only where needed, improving reliability for cold regions without universally increasing latency across all memory operations.
Solution Approach 2:
The patent implements periodic error correction operations specifically for infrequently accessed memory regions, rather than continuous correction for all regions. By scheduling error correction at periodic intervals for cold regions while maintaining standard access handling for hot regions, the system improves reliability for error-prone areas without causing latency penalties during normal operation of frequently accessed data.
2Reliability
If periodic error correction operations are performed on all memory regions, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent differentiates error correction application by memory region characteristics. Infrequently accessed regions receive periodic error correction to prevent data degradation, while frequently accessed regions rely on standard error handling mechanisms. This localized approach reduces overall power consumption compared to universal periodic correction, as energy-intensive correction operations are performed only on cold regions where they are most needed.
Solution Approach 2:
By implementing periodic rather than continuous error correction for infrequently accessed memory regions, the patent reduces power consumption. The periodic execution of correction operations allows the system to maintain reliability for cold regions while avoiding the continuous energy expenditure that would result from constant correction monitoring across all memory regions.
3Reliability
If error correction is performed during normal memory operations, then reliability is improved, but bandwidth is consumed
Solution Approach 1:
The patent extracts error correction operations from the normal memory access path for infrequently accessed regions. Instead of performing error correction during every read/write operation to all memory regions, the system separates correction functionality into periodic background operations for cold regions. This extraction prevents bandwidth consumption during normal operations while maintaining reliability through scheduled correction cycles.
Solution Approach 2:
The patent implements periodic error correction for infrequently accessed memory regions independent of normal access operations. By scheduling correction at periodic intervals rather than coupling it with every access, the system maintains reliability without consuming bandwidth during standard memory transactions. The periodic correction operates in the background without interfering with the data throughput of active memory regions.
Data Source
AI summary
Methods, systems, and devices for techniques for memory error correction are described. A memory device may operate cycles associated with refresh operations and cycles associated with refresh with error correction (ECC) operations independently. For example, the memory device may include an ECC patrol block having an error correction counter which indicates a row on which to perform an error correction procedure. Additionally, the memory device may include a refresh counter which indicates a row on which to perform a refresh operation. In response to receiving a command of a first, the memory device may modify the error correction counter and maintain the refresh counter. Alternatively, in response to receiving a command of a second, the memory device may modify the refresh counter and maintain the error correction counter.