Memory Error Correction Circuit Refresh Exclusion Logic

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Solution Overview

Problem

As semiconductor memory devices increase in capacity, it becomes challenging to fabricate memory devices without defective memory cells, leading to the need for error correction and redundant cell replacement methods.

Innovation Solution

A memory system incorporating a refresh-excluded region, error correction circuit, error check operation control circuit, bad region classifying circuit, and blocking circuit to efficiently check and correct errors, preventing the classification of refresh-excluded regions as bad regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If error check operation is performed on all memory regions, then error detection capability is improved, but refresh-excluded regions are incorrectly classified as bad regions

Engineering Contradiction:
Improveerror detection capabilityVSAvoidregion classification accuracy
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent extracts refresh-excluded regions from the error check operation by obtaining region information from a refresh mask table and comparing it with error check addresses. This separation allows the error check to be performed on valid memory regions while excluding refresh-excluded regions, preventing their incorrect classification as bad regions.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a region determination circuit as an intermediary between the error check operation control circuit and the bad region classifying circuit. This circuit determines whether the current memory region is a refresh-excluded region and provides this information to prevent misclassification, acting as a mediator that resolves the conflict between error detection and accurate region classification.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If memory capacity is increased, then storage capability is improved, but the likelihood of defective memory cells increases

Engineering Contradiction:
Improvememory capacityVSAvoiddefective cell rate
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent performs preliminary identification of refresh-excluded regions before the error check operation using the refresh mask table. By determining which regions are excluded in advance and providing this information to the bad region classifying circuit, the system prevents premature classification of these regions as bad, ensuring reliable operation even in high-capacity memory devices with increased likelihood of defective cells.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12032439B2Memory including error correction circuit and operation method of memory
Publication Date: 2024.07.09 SK HYNIX INC
  • US12032439B2 patent drawing
  • US12032439B2 patent drawing
  • US12032439B2 patent drawing

AI summary

A memory includes: a memory core including memory regions; a refresh-excluded region storing circuit storing therein information on a refresh-excluded region on which a refresh operation is not to be performed among the memory regions; an error correction circuit correcting an error in data read from the memory core based on an error correction code read from the memory core; an error check operation control circuit performing an error check operation of checking an error in the read data by using the error correction circuit; a bad region classifying circuit classifying a selected memory region as a bad region based on an error, which is detected in data read from the selected memory region during the error check operation; and a blocking circuit preventing the bad region classifying circuit from classifying the refresh-excluded region as a bad region based on the information.