Semiconductor Memory Error Correction for Retention-Time Power Savings

Solution Overview

Problem

Existing nonvolatile semiconductor memory devices face inefficiencies due to the use of high-performance error correction mechanisms that waste power and resources, even when data retention time is short, and require large correction targets, leading to unnecessary power consumption and circuit size.

Innovation Solution

A semiconductor memory device with a dual error correction system, comprising first and second error correction units with varying capabilities, where the first unit corrects errors using low-power Hamming codes for short retention times and the second unit uses high-capability codes like BHC or RS codes for longer retention times, reducing power consumption and circuit size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a high-performance error correction mechanism is used to guarantee correct information restoration after long retention, then error correction capability is improved, but power consumption increases

Engineering Contradiction:

Improveerror correction capabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic error correction capability selection based on retention time. The error correction unit adaptively changes its correction capability according to the actual retention time of data in the memory device. When retention time is short, lower correction capability is used; when retention time is long, higher correction capability is activated. This dynamic adaptation resolves the contradiction by matching error correction resources to actual needs, reducing unnecessary power consumption while maintaining reliability.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of error correction capability based on retention time conditions. By monitoring or estimating the retention time, the system adjusts the error correction level (e.g., switching between different correction codes or correction intensities). This parameter change allows the system to optimize the balance between reliability and power consumption by using only the necessary correction capability for each data access operation.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If a high-performance error correction mechanism is used to correct multiple errors, then error correction capability is improved, but circuit scale increases

Engineering Contradiction:

Improveerror correction capabilityVSAvoidcircuit scale

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic error correction capability selection based on retention time. The error correction unit adaptively changes its correction capability according to the actual retention time of data in the memory device. When retention time is short, lower correction capability is used; when retention time is long, higher correction capability is activated. This dynamic adaptation resolves the contradiction by matching error correction resources to actual needs, reducing unnecessary power consumption while maintaining reliability.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of error correction capability based on retention time conditions. By monitoring or estimating the retention time, the system adjusts the error correction level (e.g., switching between different correction codes or correction intensities). This parameter change allows the system to optimize the balance between reliability and power consumption by using only the necessary correction capability for each data access operation.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If error correction is performed with high capability regardless of retention time, then reliability is improved, but power is wasted when data is accessed frequently

Engineering Contradiction:

Improveinformation restoration accuracyVSAvoidwasted power

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent implements dynamic error correction capability selection based on retention time. The error correction unit adaptively changes its correction capability according to the actual retention time of data in the memory device. When retention time is short, lower correction capability is used; when retention time is long, higher correction capability is activated. This dynamic adaptation resolves the contradiction by matching error correction resources to actual needs, reducing unnecessary power consumption while maintaining reliability.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of error correction capability based on retention time conditions. By monitoring or estimating the retention time, the system adjusts the error correction level (e.g., switching between different correction codes or correction intensities). This parameter change allows the system to optimize the balance between reliability and power consumption by using only the necessary correction capability for each data access operation.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20250365021A1Semiconductor memory device and method of controlling the same

Publication Date: 2025.11.27 KIOXIA CORP

AI summary

A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.