Memory Error Coalescing with Crossbar Bit Steering
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Solution Overview
Problem
Random bit errors in memories negatively impact the robustness and availability of computer systems, as existing technologies fail to effectively manage and correct these errors across multiple bit positions within codewords.
Innovation Solution
A programmable crossbar matrix or array of steering multiplexors coalesces data from multiple 'bad' bit positions into a single codeword symbol, utilizing error mapping information to configure the routing logic at boot or initialization time, and distributing the steering logic between the memory controller, data buffers, and memory devices to improve error detection and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data from multiple bad bit positions is distributed across multiple codeword symbols, then the memory system can store more data, but error detection and correction capability is reduced
Solution Approach 1:
The patent merges data from multiple bad bit positions into a single codeword symbol. The coalescing logic consolidates bits from different data symbol locations that correspond to unreliable memory positions and places them together in one target symbol, enabling the EDC circuitry to detect and correct errors more effectively while maintaining storage capacity.
Solution Approach 2:
The patent introduces coalescing logic as an intermediary component between the memory array and the EDC circuitry. This intermediary performs bit repositioning by routing data from multiple bad bit positions to a consolidated location, allowing the EDC system to handle errors more efficiently without reducing overall storage capacity.
2Reliability
If steering logic is implemented in the memory controller, then error coalescing capability is improved, but device complexity increases
Solution Approach 1:
The patent implements steering logic within the memory controller that serves multiple functions: it performs error coalescing for EDC, supports dynamic reconfiguration based on bad bit patterns, and can adapt to different memory ranks and configurations. This multi-functionality justifies the added complexity by providing comprehensive error management capabilities.
Solution Approach 2:
The patent employs dynamically reconfigurable steering logic that can adapt its routing patterns based on detected bad bit positions. The system configures the steering logic at initialization based on error mapping information and can reconfigure as needed, making the complexity adaptive rather than static and allowing optimization for specific error patterns.
3Reliability
If bad bit positions are identified and managed, then error correction is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary identification and mapping of bad bit positions during memory initialization or manufacturing testing. The error mapping information is stored and used to pre-configure the steering logic, so that when errors occur during normal operation, the system can immediately apply the appropriate coalescing pattern without needing to reanalyze bit positions.
Data Source
AI summary
A programmable crossbar matrix or an array of steering multiplexors (MUXs) coalesces (i.e., routes) the data values from multiple known “bad” bit positions within multiple symbols of a codeword, to bit positions within a single codeword symbol. The single codeword symbol receiving the known “bad” bit positions may correspond to a check symbol (vs. a data symbol). Configuration of the routing logic may occur at boot or initialization time. The configuration of the routing logic may be based upon error mapping information retrieved from system non-volatile memory (e.g., memory module serial presence detect information), or from memory tests performed during initialization. The configuration of the routing logic may be changed on a per-rank basis.