Semiconductor Memory Error Detection Code Generator Layout
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Solution Overview
Problem
Conventional semiconductor memory devices face increased layout area and signal transmission delays due to the placement of error detection code generators, which necessitate longer signal lines and inefficient data transmission.
Innovation Solution
The semiconductor memory device employs multiple error detection code generators with cyclic redundancy check code circuits and XOR operations to generate error detection codes, allowing for the combination of bits from different error detection codes to produce final error detection signals, while maintaining error detection ability without increasing layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the error detection code generator is disposed in a region between memory cell array blocks, then error detection capability is maintained, but layout area increases and signal transmission delays occur
Solution Approach 1:
The patent divides the error detection code generation function into multiple separate generators, each responsible for specific data blocks. This segmentation allows each generator to be positioned closer to its associated data blocks, reducing the need for long signal lines and minimizing layout area while maintaining comprehensive error detection coverage across all memory blocks.
Solution Approach 2:
The patent reorganizes the spatial arrangement of error detection code generators from a centralized location to a distributed arrangement adjacent to respective data blocks. This dimensional repositioning reduces signal line lengths by placing generators in optimal locations near their data sources, thereby reducing layout area without compromising error detection capability.
2Reliability
If the error detection code generator is disposed in a region between memory cell array blocks, then error detection capability is maintained, but signal transmission delays increase
Solution Approach 1:
By segmenting the error detection code generation function into multiple distributed generators, the patent reduces the distance data signals must travel to reach the generator. This segmentation eliminates the need for long signal lines that would cause transmission delays, while each generator maintains error detection for its specific data blocks.
Solution Approach 2:
The patent positions error detection code generators as intermediary elements directly adjacent to their associated data blocks, eliminating the need for distant signal routing. This intermediary placement acts as a local processing point that reduces signal transmission path length and associated delays while maintaining error detection functionality.
3Area of stationary object
If multiple error detection code generators are used, then layout area is reduced and signal transmission is improved, but device complexity increases
Solution Approach 1:
The patent divides the error detection system into multiple independent generators, each handling specific data blocks. This segmentation reduces layout area by eliminating long signal lines, and while it increases the number of components, each generator is a standardized unit that can be implemented using identical circuitry, thereby managing complexity through modularity and repetition rather than unique complex designs.
Data Source
AI summary
A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device may include a first memory cell array block generating first data, a second memory cell array block generating second data, and first and second error detection code generators. The first error detection code generator may generate a first error detection code and may combine a portion of bits of the first error detection code with a portion of bits of a second error detection code to generate a first final error detection signal. The second error detection code generator may generate the second error detection code and may combine the remaining bits other than the portion of bits of the second error detection code with the remaining bits other than the portion of bits of the first error detection code to generate a second final error detection signal.