Semiconductor Memory Error Detection via Multiplexer and EDC Generator
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Solution Overview
Problem
Conventional semiconductor memory apparatuses lack the capability to detect and correct errors in data transmission between the graphic processing unit (GPU) and the semiconductor memory apparatus, leading to potential fatal errors due to increased error probability at high data transmission speeds.
Innovation Solution
Incorporation of a memory cell block, data input/output units, global data lines, multiplexers, and an error detection code generator to detect errors in data transmission, utilizing error detection codes such as cyclic redundancy check (CRC) to identify and output error detection codes, thereby enabling error detection and correction during data input/output operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transmission speed is increased to achieve higher memory capacity and performance, then productivity is improved, but error probability in data transmission increases
Solution Approach 1:
The patent implements error detection through feedback mechanisms by generating error detection codes (EDC) based on transmitted data and comparing them with received data. The EDC generator creates parity bits that are transmitted alongside data, allowing the receiving end to detect and report transmission errors, thereby providing feedback about data integrity without requiring retransmission of the entire data stream.
Solution Approach 2:
The patent introduces error detection codes as an intermediary element between the transmitted data and the receiving end. These EDCs act as mediators that carry information about data integrity independently from the actual data stream, enabling error detection without interfering with the primary data transmission function or requiring changes to the fundamental transmission protocol.
2Reliability
If error detection capability is added to detect transmission errors, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the error detection function with the existing data transmission infrastructure by integrating EDC generation into the same circuit blocks that handle data processing. The error detection codes are generated using the same timing signals and data paths as the main data transmission, combining multiple functions into unified circuit modules rather than adding separate independent error detection systems.
Solution Approach 2:
The patent designs the error detection mechanism to serve multiple functions: it detects errors during both read and write operations, works with both serial and parallel data modes, and can operate in different error detection modes (such as CRC and parity check). This multi-functionality reduces the need for separate dedicated error detection circuits for different operational scenarios.
Data Source
AI summary
A semiconductor memory apparatus capable of detecting an error in data input/output includes a memory cell block including a plurality of memory cells. A data input unit receives data from outside the semiconductor memory apparatus and performs predetermined signal processing to record the received data in the memory cell block. A first global data line is connected between the data input unit and the memory cell block. A data output unit receives data from the memory cell block and performs predetermined signal processing to output the received data to the outside of the semiconductor memory apparatus. A second global data line is connected between the memory cell block and the data output unit. A multiplexer selectively outputs data from the first or second global data line in response to a control signal. An error detection code generator generates an error detection code having a plurality of bits to detect whether the data output from the multiplexer includes an error, and outputs the error detection code to the outside of the semiconductor memory apparatus.