Memory Error Rate Detection Queuing During Host Idle Periods
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Solution Overview
Problem
Performing error rate detection procedures in memory systems during active times increases latency in servicing memory access commands from the host system, negatively impacting user experience.
Innovation Solution
Performing at least some error rate detection procedures in the background during idle times based on triggering conditions, allowing the memory system to utilize resources for memory access operations during active times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error rate detection procedures are performed during active times, then error detection is completed timely, but latency in servicing memory access commands increases
Solution Approach 1:
The system performs error rate detection procedures in advance during idle times before they are strictly needed, storing results for later use. This allows the detection to be completed proactively without interfering with subsequent memory access operations, thus maintaining reliability while avoiding latency penalties during active servicing periods
Solution Approach 2:
The system dynamically adjusts the timing of error rate detection procedures based on system state, switching between foreground execution during idle periods and background execution during active periods. This dynamic scheduling allows the system to optimize between detection timeliness and memory access latency by adapting to real-time workload conditions
2Reliability
If error rate detection procedures are performed in the foreground, then detection resources are prioritized, but memory access command servicing latency increases
Solution Approach 1:
The system implements periodic error rate detection procedures that are scheduled during idle periods rather than continuously interrupting memory access operations. This periodic approach ensures error detection is performed regularly to maintain reliability while concentrating detection resources only when memory access productivity is not compromised
Solution Approach 2:
Error rate detection is performed in advance during idle foreground periods when the system is not servicing memory commands, allowing the detection to complete with high priority resource allocation before the system transitions to high-productivity memory access mode, thus avoiding conflicts between detection priority and servicing speed
Data Source
AI summary
Methods, systems, and devices for efficient performance of error rate detection procedures in a memory system are described. A memory system may determine whether a condition for performing an error rate detection procedure has been satisfied. Based on determining that the condition has been satisfied, the memory system may add a request for the error rate detection procedure to a queue. The memory system may then perform the error rate detection procedure indicated by the request in the queue based on determining that access activity from a host system has lapsed for a threshold duration.