Memory Error Detection via Dual Circuit Segmentation
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Solution Overview
Problem
Current methods for reading and writing data in memory systems are prone to errors, particularly during the writing process, where data can be inadvertently or intentionally written at incorrect addresses, necessitating more reliable error detection and correction mechanisms.
Innovation Solution
The proposed solution involves using two identical memory circuits to store equal-sized parts of a binary word, with internal control signals compared to detect errors, and employing an error correcting or detecting code that is representative of the data and address, allowing for redundancy checks to ensure accurate data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is stored in a single memory circuit, then the device complexity is low, but the reliability of data storage is reduced
Solution Approach 1:
The binary word is divided into at least two parts of equal size, with each part stored in a separate identical memory circuit. This segmentation allows for independent verification of each part, enabling error detection while distributing the complexity across multiple simpler storage units rather than requiring a single complex error-correcting system.
Solution Approach 2:
Identical copies of the data parts are created and stored in separate memory circuits. By comparing these copies through internal control signals, the system can detect writing errors without requiring complex real-time validation logic, thus improving reliability while keeping the overall device complexity manageable.
2Reliability
If error detection mechanisms are added to memory operations, then the reliability of data storage is improved, but the productivity of data writing and reading operations is reduced
Solution Approach 1:
Error detection is performed during the writing operation itself by comparing internal control signals of identical memory circuits before the data is considered successfully stored. This preliminary verification prevents erroneous data from being committed to the system, ensuring reliability without requiring separate post-writing validation steps that would reduce productivity.
Solution Approach 2:
The memory system performs self-verification by comparing its own internal control signals during normal operation. The identical memory circuits serve their primary storage function while simultaneously providing error detection capability through their inherent signal comparisons, eliminating the need for separate dedicated error detection hardware that would slow down operations.
3Reliability
If internal control signals are compared between memory circuits, then writing errors are detected, but the device complexity increases
Solution Approach 1:
The internal control signals generated during normal memory operations serve dual purposes: they control the standard write/read functions and simultaneously provide data for error detection through comparison between identical circuits. This multi-functionality allows error detection without adding separate dedicated signal paths or comparison hardware, thus detecting writing errors while minimizing increases in device complexity.
4Reliability
If error correcting codes are used, then the reliability of data retrieval is improved, but the loss of time for data processing increases
Solution Approach 1:
The patent replaces complex mechanical or algorithmic error correction processes with a simpler signal comparison mechanism. By comparing internal control signals between identical memory circuits during normal operations, the system achieves error detection without requiring time-consuming error correction algorithms or additional processing steps, thus maintaining fast data retrieval while improving reliability.
Data Source
AI summary
A method for detecting a reading error of a datum in memory. A binary word which is representative of the datum and an error correcting or detecting code is read by: reading a first part of the binary word stored at a first address in a first memory circuit; and reading a second part of the binary word stored at a second address in a second memory circuit. The first and second parts read from the first and second memory circuits, respectively, are concatenated to form a read binary word. The datum is then obtained by removing the error correcting or detecting code from the read binary word. A new error correcting or detecting code is calculated from the obtained datum and compared to the removed error correcting or detecting code to detect error in the obtained datum.