Memory Error Detection Trigger Circuit for Soft Error Prevention
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Solution Overview
Problem
Current methods for detecting soft errors in memory devices, such as SRAM and DRAM, are either overly resource-intensive, inefficient in terms of latency, or fail to detect errors until data is accessed, leading to potential data corruption and system instability, especially in environments like mobile devices and automobiles.
Innovation Solution
A storage device with an error detection system that performs Error Detection Code (EDC) or Error Correction Code (ECC) operations cyclically, regardless of data access, using an error detection trigger circuit to initiate error detection at set intervals or upon mode changes, ensuring quick error detection and reporting to prevent additional errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection is performed continuously or frequently, then error detection speed and reliability are improved, but power consumption and processing overhead increase
Solution Approach 1:
The patent implements periodic error detection by triggering EDC/ECC operations at specific intervals or under certain conditions (e.g., when data is written to volatile memory, when transitioning between active and retention modes, or at predetermined time intervals). This periodic approach ensures errors are detected reliably while avoiding continuous detection that would waste power, thus resolving the contradiction between detection reliability and power consumption.
Solution Approach 2:
The patent dynamically adjusts error detection parameters such as detection frequency, trigger conditions, and operational modes based on system state (e.g., active vs. retention mode, data access patterns). By changing these parameters adaptively, the system maintains high error detection reliability when needed while reducing power consumption during low-risk periods, effectively balancing the two conflicting requirements.
2Use of energy by moving object
If error detection is performed only when data is accessed, then power consumption is reduced, but error detection latency increases and errors may go undetected
Solution Approach 1:
The patent performs error detection in advance before data is actually accessed or before the system transitions to a low-power state. By proactively detecting errors while data is still in volatile memory or before potential corruption occurs, the system minimizes detection latency without requiring continuous monitoring, thus reducing power consumption while maintaining timely error detection.
Solution Approach 2:
The patent maintains continuous error protection capability through periodic detection triggers that ensure error detection capability is always available without requiring continuous active detection. The system continuously monitors for detection trigger conditions (e.g., write operations, mode transitions) and automatically initiates detection when appropriate, ensuring no errors go undetected while minimizing active detection time and power consumption.
3Reliability
If comprehensive error detection is performed on all data, then detection coverage is improved, but processing overhead and system complexity increase
Solution Approach 1:
The patent applies error detection selectively to specific data portions or memory regions based on their importance, volatility, or risk of corruption. For example, it prioritizes detection for data in volatile memory, frequently accessed data, or critical system data, while reducing detection frequency for less critical data. This localized approach ensures comprehensive coverage of high-risk areas without the processing overhead of detecting every single data element uniformly.
Solution Approach 2:
The patent divides the error detection process into segments or stages, performing detection on different data portions at different times or using different detection methods. This segmentation allows the system to manage processing overhead by breaking down comprehensive detection into smaller, more manageable tasks that can be executed efficiently without overwhelming system resources, while still achieving overall comprehensive coverage.
Data Source
AI summary
A device for detecting an error of data stored in a memory device includes an error detection trigger circuit configured to transmit an error detection trigger information for instructing an error detecting operation for at least a part of the data, at each first cycle, in the case where an error detection performing condition is satisfied; an error detection performing circuit configured to receive the error detection trigger information, instruct an error calculation engine to perform an error detecting operation for part or all of the data, and receive an error detection result information from the error calculation engine; and a reporting circuit configured to transmit reporting information depending on the error detection result information, to a target device.