Memory Error Correction Using Dual Detection Algorithms

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Solution Overview

Problem

Current memory systems face limitations in error correction ability, which affects the reliability and efficiency of data processing due to the trade-off relationship between error correction capabilities and system performance.

Innovation Solution

Implementing an error correction apparatus with dual error detection algorithms, where a first algorithm detects up to L errors and a second algorithm detects up to K errors (K > L), allowing for enhanced error detection and correction capabilities, including the use of Peterson, Berlekamp-Massey, and Reed-Solomon codes, to improve data reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single error correction algorithm with high error detection capability (K errors) is used, then the reliability of data correction is improved, but the time required for error detection and correction increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoiderror detection and correction time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The error detection process is segmented into two independent algorithms with different detection capabilities (L errors and K errors). The controller executes the first algorithm (Peterson or Berlekamp-Massey) which is faster but detects fewer errors, and the second algorithm (Reed-Solomon) which is slower but detects more errors. This segmentation allows the system to achieve high reliability through the second algorithm while maintaining efficiency through the first algorithm for cases with fewer errors.

Inventive Principle:
Principle #1Segmentation

2Reliability

If multiple error detection algorithms are implemented, then the range of detectable errors is expanded, but the complexity of the error correction apparatus increases

Engineering Contradiction:
Improveerror detection rangeVSAvoiderror correction apparatus complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges two different error detection algorithms (first algorithm with L error detection and second algorithm with K error detection) into a unified error correction apparatus. The controller integrates both algorithms and implements a coordination mechanism that selects which algorithm to execute based on system needs, thereby expanding the error detection range while managing complexity through structured integration.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The error correction apparatus employs dynamic algorithm selection where the controller can choose between executing the first error detection algorithm or the second error detection algorithm based on the specific situation. This dynamic approach allows the system to adapt its complexity level - using the simpler first algorithm when sufficient, and the more capable second algorithm when needed - thereby managing device complexity while maintaining expanded error detection capability.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11095310B2Error correction apparatus, operation method thereof and memory system using the same
Publication Date: 2021.08.17 SK HYNIX INC
  • US11095310B2 patent drawing
  • US11095310B2 patent drawing
  • US11095310B2 patent drawing

AI summary

An error correction apparatus may include: an input component configured to receive data; an error information generation component having a first error detection ability to detect L errors and a second error detection ability to detect K errors, where L is a positive integer and K is an integer larger than L, and configured to generate error information including the number of errors contained in the received data and the positions of the errors, based on the first error detection ability, and generate the error information based on the second error detection ability, when the error information is not generated on the basis of the first error detection ability; an error correction component configured to correct the errors of the received data based on the generated error information; and an output component configured to output the corrected data.