Multi-Level Memory Error Correction via Error-to-Erasure Coding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing error correction techniques in memory devices face challenges in achieving high code rates without increasing processing time and latency, particularly in correcting errors in multi-level cell memory systems.
Innovation Solution
The implementation of a tensor product code that combines single parity check and Bose-Chaudhuri-Hocquenghem codes, along with low-density parity check codes, to identify and convert errors into erasures, allowing for higher code rates and efficient error correction in memory systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If higher code rates are used to improve error correction efficiency, then processing time and latency increase
Solution Approach 1:
The patent segments the error correction process into multiple stages: first converting errors to erasures using tensor product codes, then correcting erasures using LDPC codes. This segmentation allows each stage to be optimized independently, achieving high code rates without proportionally increasing processing time.
Solution Approach 2:
The patent introduces an intermediary conversion step that transforms the memory channel from errors-only to erasures-only. This intermediary transformation enables the use of more efficient erasure correction codes, improving overall error correction efficiency while managing processing time.
2Reliability
If more redundant information bits are added to improve error correction capability, then code rate decreases
Solution Approach 1:
The patent divides redundancy into two functional parts: tensor product code redundancy for error-to-erasure conversion, and LDPC code redundancy for erasure correction. This segmentation allows optimized redundancy allocation where each code type uses minimal redundancy for its specific function, maximizing code rate while maintaining error correction capability.
Solution Approach 2:
The patent changes the parameter representation of errors by converting them to erasures. This parameter change enables the system to achieve the same error correction capability with different redundancy requirements, improving code rate efficiency.
3Productivity
If tensor product codes combining single parity check and BCH codes are used to convert errors to erasures, then code rate increases and error correction efficiency improves
Solution Approach 1:
The patent merges single parity check codes and BCH codes into a tensor product code structure. This combination creates a unified error-to-erasure conversion mechanism that achieves high code rates while managing complexity through the systematic integration of complementary code properties.
Data Source
AI summary
Embodiments of the present invention disclose methods and apparatuses for correcting errors in data stored in a solid state device. The solid state device may have a plurality of bits stored in multi-level memory cells. The method may include identifying one or more errors in a plurality of memory cells. The method may further include converting the erroneous cells to erasures. The method may further include correcting the one or more erasures.