Non-Volatile Memory Error Correction Across Faulty Devices
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Solution Overview
Problem
Non-volatile memory systems in electronic devices experience read errors due to storage media and signal processing errors, necessitating effective error correction techniques to manage data integrity across multiple memory devices.
Innovation Solution
Implementing error correction codes such as Bose-Chaudhuri-Hocquenghem (BCH) and Reed-Solomon codes across multiple memory devices, with a bitwise XOR mechanism to distribute codewords and recover data from faulty devices, allowing for sequential testing and correction of memory devices to ensure data integrity during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction codes are implemented across multiple memory devices, then data integrity is improved, but device complexity increases
Solution Approach 1:
The patent divides the error correction system into multiple independent memory devices, each storing portions of data and error correction codewords. The data is segmented across N memory devices, with each device handling a specific portion independently, allowing parallel error correction operations and reducing the complexity burden on any single device.
Solution Approach 2:
The patent introduces an intermediary bitwise XOR operation that combines information from multiple memory devices to recover data. This XOR mechanism acts as a mediator that simplifies the error correction process by providing a straightforward mathematical operation to reconstruct lost or corrupted data without requiring complex decoding algorithms in each individual device.
2Reliability
If sequential testing and correction of memory devices is performed, then reliability is improved, but loss of time increases
Solution Approach 1:
The patent performs preliminary error correction by retrieving and testing error correction codewords from each memory device before attempting to retrieve the actual data. This preliminary action identifies faulty devices early in the process, allowing the system to skip unnecessary data retrieval operations from defective devices and reduce overall time loss.
Solution Approach 2:
The patent implements a staged error correction approach where only the necessary portion of memory devices are fully tested and corrected. If error correction succeeds after testing a subset of devices, the system stops further testing, performing only the partial action needed rather than exhaustively testing all devices, thus reducing time loss while maintaining reliability.
Data Source
AI summary
Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a memory controller comprises logic to receive a read request for data stored in a memory, retrieve the data and at least one associated error correction codeword, wherein the data and an associated error correction codeword is distributed across a plurality of memory devices in memory, apply a first error correction routine to decode the error correction codeword retrieved with the data and in response to an uncorrectable error in the error correction codeword, apply a second error correction routine to the plurality of devices in memory. Other embodiments are also disclosed and claimed.