Memory Device Error-Handling Flow Management with Probability Data

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Solution Overview

Problem

Conventional memory sub-systems employ static error-handling flows that do not adapt to changing operating conditions, leading to inefficiencies such as increased latency and power consumption, without considering system latency and throughput under varied workload stress conditions.

Innovation Solution

Implementing a memory sub-system controller that optimizes error-handling operations using a probability data structure, which calculates the order of error-handling operations based on pass and fail counts and latency data, dynamically adjusting the error-handling flow to minimize latency and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If static error-handling flows are used in memory sub-systems, then the system structure is simple and easy to implement, but the latency increases and power consumption increases under varied workload conditions

Engineering Contradiction:
Improveerror-handling flow structureVSAvoiderror-handling latency
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent implements dynamic error-handling flows that adapt to changing operating conditions and workload stress levels. The system transitions from static, predetermined error-handling sequences to dynamic sequences that are selected based on real-time monitoring of workload conditions, error types, and system state, thereby reducing latency without excessive complexity

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes operational parameters by adjusting error-handling flow selection based on workload stress conditions, error recovery probabilities, and latency requirements. Different error-handling flows are activated depending on the current operating parameters, allowing optimization of latency and power consumption for each specific condition

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If static error-handling flows are used in memory sub-systems, then the system structure is simple and easy to implement, but the power consumption increases under varied workload stress conditions

Engineering Contradiction:
Improveerror-handling flow structureVSAvoidpower consumption
Core Design Contradiction:
Device complexityVSUse of energy by stationary object

Solution Approach 1:

The system dynamically selects error-handling flows based on workload conditions to optimize power consumption. By monitoring system state and workload stress levels, the controller activates appropriate error-handling sequences that minimize energy usage while maintaining effective error recovery, avoiding the continuous high power consumption of static approaches

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system adjusts power consumption parameters by selecting different error-handling flows optimized for specific workload conditions. The controller modifies operational parameters such as error-checking intensity and recovery sequence selection based on real-time power management requirements and workload characteristics

Inventive Principle:
Principle #35Parameter changes

3Loss of time

If dynamic error-handling flows are implemented based on probability data structure, then the latency is reduced and power consumption is reduced, but the device complexity increases

Engineering Contradiction:
Improveerror-handling latencyVSAvoiderror-handling flow management
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The system implements feedback mechanisms by monitoring error-handling outcomes, workload conditions, and system performance metrics. This feedback is used to update probability data structures and refine flow selection decisions, enabling the system to learn from past operations and optimize latency without requiring excessively complex manual configuration

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The error-handling system serves itself by automatically selecting and optimizing flow sequences based on embedded probability data structures. The system autonomously adapts to changing conditions using pre-characterized workload profiles and real-time monitoring, reducing the need for external intervention and managing complexity through self-organization

Inventive Principle:
Principle #25Self-service

4Use of energy by stationary object

If dynamic error-handling flows are implemented based on probability data structure, then the power consumption is reduced, but the device complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoiderror-handling flow management
Core Design Contradiction:
Use of energy by stationary objectVSDevice complexity

Solution Approach 1:

The system performs preliminary actions by pre-characterizing workload conditions and pre-computing probability data structures during system initialization or idle periods. This advance preparation enables rapid, low-power flow selection during actual operation without requiring complex real-time computations, thereby reducing operational power consumption while managing complexity through offline preparation

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system autonomously manages its own error-handling optimization by using embedded probability data structures to self-select appropriate flows based on monitored conditions. This self-service capability reduces the need for complex external control mechanisms and minimizes power consumption during flow selection decisions

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20250298520A1Management of error-handling flows in memory devices using probability data structure
Publication Date: 2025.09.25 MICRON TECHNOLOGY INC
  • US20250298520A1 patent drawing
  • US20250298520A1 patent drawing
  • US20250298520A1 patent drawing

AI summary

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including determining an optimized order of a set of error-handling operations based on a result of testing using sample data, wherein the sample data is tested through each of the set of error-handling operations performed on data residing in a segment of the memory device in an existing order, and wherein the optimized order comprises an adjustment to an order of one or more error-handling operations of the set of error-handling operations in the existing order; and executing the set of error-handling operations in the optimized order to correct one or more errors in the data stored on the memory device.