Nonvolatile Memory Error Management via Hierarchical Cell Checking
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Solution Overview
Problem
Nonvolatile memory devices, such as flash memory, face challenges in reliability due to frequent write operations leading to inefficient data retention and read disturbance issues, where data errors are not effectively managed, potentially causing damage to storage blocks.
Innovation Solution
Implementing a control unit with error checking and correcting codes, such as LDPC, to identify and correct errors in first-level cells within second-level cells, and proactively copying valid data from damaged blocks to maintain data integrity by designating and relocating damaged physical or logical units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If frequent write operations are performed in nonvolatile memory, then data storage capacity and operation speed are improved, but data retention efficiency deteriorates and read disturbance issues occur
Solution Approach 1:
The patent performs preliminary error detection by reading a first cell and checking for errors before they propagate. When errors are detected in the first cell, the system proactively checks other cells in the same block before they become problematic, preventing cascading failures and maintaining data integrity despite frequent write operations.
Solution Approach 2:
The patent implements a feedback mechanism where error detection results from reading the first cell trigger subsequent error checking in other cells. This feedback loop allows the system to dynamically adjust its error management strategy based on actual error conditions, improving reliability without significantly impacting write operation performance.
2Reliability
If error checking is performed on every read operation, then data reliability is improved, but read operation speed deteriorates
Solution Approach 1:
The patent applies partial error checking by first examining a single cell and only expanding to check other cells in the block when errors are detected in the initial cell. This selective approach maintains high read speeds for error-free data while providing comprehensive error detection when needed, resolving the contradiction between reliability and speed.
3Reliability
If error checking and correcting codes are implemented, then data integrity is improved, but device complexity increases
Solution Approach 1:
The patent segments the error checking process into hierarchical levels: first checking a single cell, then conditionally checking other cells in the block only when errors are detected. This segmentation reduces the average complexity of the control unit by avoiding unnecessary comprehensive checks, while still maintaining high data integrity through targeted error detection when needed.
Data Source
AI summary
A data storage device with high security is disclosed. A nonvolatile memory provides a storage space divided into a plurality of first-level cells. The first-level cells are grouped into a plurality of second-level cells with each second-level cell containing several first-level cells. Each of the plurality of first-level cells is provided with checking and correcting code by a control unit. When reading a specified first-level cell, the control unit checks data in the specified first-level cell based on the checking and correcting code of the specified first-level cell and thereby performs a self-test on another space of a specified second-level cell. The specified first-level cell is provided in the specified second-level cell.