Semiconductor Memory Error Detection and Idle Rewrite
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Solution Overview
Problem
Semiconductor memory devices face delays in processing due to write and read operations when errors occur, leading to potential real-time property violations and increased error bits, especially when throughput is critical.
Innovation Solution
Incorporating a data comparator, address comparator, and selector within the semiconductor memory device to compare and validate data before and after writing, allowing for immediate operation even with detected errors, and performing rewrite operations during idle periods to prevent interruptions in write and read processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a rewrite operation is performed immediately when an error is detected, then data accuracy is improved, but processing speed and real-time performance deteriorate
Solution Approach 1:
The patent performs preliminary error detection by comparing written data with read-back data immediately after writing. When an error is detected, the system prepares correction data in advance but delays the actual rewrite operation until an idle period occurs, thus maintaining data accuracy while avoiding immediate processing interruptions.
Solution Approach 2:
The patent dynamically adjusts the timing of rewrite operations based on system state. Instead of a fixed immediate rewrite policy, the system flexibly schedules rewrite operations during idle periods when the memory device is not being accessed, optimizing both reliability and speed based on real-time operational conditions.
2Reliability
If a rewrite operation is performed when sequentially reading or writing data, then error correction is improved, but throughput and productivity deteriorate
Solution Approach 1:
The patent extracts the rewrite operation from the critical data access path. By separating error detection from error correction timing, the system allows sequential read/write operations to proceed without interruption while handling corrections during idle periods, thus maintaining throughput while ensuring error correction.
Solution Approach 2:
The patent maintains continuous data access operations by performing rewrites during idle periods rather than interrupting sequential operations. This ensures that the useful action of data processing continues uninterrupted while error correction occurs in the background during non-critical time slots.
3Reliability
If the memory controller waits for rewrite operation completion, then data reliability is improved, but real-time performance and response time deteriorate
Solution Approach 1:
The patent performs preliminary error detection and prepares correction data in advance, but defers the actual rewrite execution until an idle period. This allows the memory controller to return control to the processor immediately after detecting an error, avoiding waiting time while ensuring the rewrite will be performed during a non-critical period to maintain reliability.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes first to fifth units. The first unit compares first data being write target data before write in a memory, with second data written in the memory and then read out. The second unit stores the first data if a data comparison result indicates mismatch. The third unit stores a write address corresponding to the write target data if the data comparison result indicates mismatch. The fourth unit compares a read address corresponding to read target data with an address stored in the third unit. The fifth unit selects data read out from the memory in accordance with the read address as the read target data if a address comparison result indicates mismatch, and selects data read out from the second unit as the read target data if the address comparison result indicates match.