Semiconductor Memory Error Injection Register Set
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Solution Overview
Problem
Reducing the size of semiconductor memory devices increases bit errors and affects yield, as existing technologies struggle to effectively manage and correct errors in high-density memory systems.
Innovation Solution
Incorporating an error injection register set and write data generator within the semiconductor memory device, which stores error bits associated with data sets and generates write data sets for error correction, allowing for controlled injection and correction of error patterns within the memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of semiconductor memory devices is reduced, then manufacturing cost and density improve, but bit error rate increases and yield deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-loading error patterns into the error injection register set before actual memory operations. The control logic proactively generates corrected write data sets by combining incoming data with stored error patterns, preventing errors from manifesting during normal operation. This advance preparation allows the system to counteract the increased bit error rate inherent in high-density memory without adding external correction hardware.
Solution Approach 2:
The memory device performs self-service through internal error correction mechanisms. The error injection register set, data input buffer, and write data generator work together within the device to automatically detect and correct errors in incoming data before it is written to the high-density memory cell array. This self-correcting capability allows the device to maintain reliability despite the increased error susceptibility of miniaturized memory cells, eliminating the need for additional external error correction hardware.
2Reliability
If error correction hardware is added to high-density memory, then reliability improves, but device complexity and cost increase
Solution Approach 1:
The patent achieves universality by designing the error injection register set and write data generator to perform multiple functions. These components not only store and inject error patterns but also serve as part of the error correction mechanism by generating corrected data sets. The control logic integrates both error injection and error correction operations within the same hardware structure, allowing the device to maintain reliability without adding separate dedicated correction hardware, thus avoiding increased device complexity.
Solution Approach 2:
The patent merges the error correction function with the existing data write path. The error injection register set, data input buffer, and write data generator are combined into an integrated error correction system that operates seamlessly with the memory write operation. By merging these functions into a unified hardware structure rather than adding separate correction circuits, the patent improves reliability while minimizing the increase in device complexity and manufacturing cost.
Data Source
AI summary
A semiconductor memory device which includes a memory cell array, an error injection register set, a data input buffer, a write data generator, and control logic. The error injection register set stores an error bit set, including at least one error bit, based on a first command. The error bit set is associated with a data set to be written in the memory cell array. The data input buffer stores the data set to be written in the memory cell array based on a second command. The write data generator generates a write data set to be written in the memory cell array based on the data set and the error bit set. The control logic controls the error injection register set and the data input buffer.