Memory Error Correction Using Layered k-Out-of-n Code Reads
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Solution Overview
Problem
Existing error correction methods in memory systems, particularly in resistive memories (RRAMs), are inefficient in differentiating between memory states and detecting errors, leading to inaccuracies in data retrieval.
Innovation Solution
A method and apparatus for error correction that involves reading a bit group of n memory cells, determining n states in a time domain for k1-out-of-n and k2-out-of-n codes, using a previously read n-bit code word of the k1-out-of-n code to identify erroneous bits, and applying an external error code to correct errors, with the use of Reed-Solomon codes for byte error detection and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single k-out-of-n code is used for error detection, then the error detection capability is limited, but the system complexity remains low
Solution Approach 1:
The patent segments the error detection task by using multiple k-out-of-n codes with different k values (k1, k2, ..., km) where each code provides a different level of error detection capability. The memory system is divided into multiple code spaces, allowing progressive error detection from simple to complex error patterns without requiring a single overly complex code.
Solution Approach 2:
The patent implements a universal error detection mechanism that handles multiple types of errors (single-bit, multi-bit, pattern-based) using a unified multi-code framework. The same decoding logic processes different k-out-of-n codes, providing multi-functionality in error detection without requiring separate specialized circuits for each error type.
2Measurement precision
If multiple k-out-of-n codes with different k values are used, then error detection accuracy improves, but the number of code words increases significantly
Solution Approach 1:
The patent adds a new dimension to the code space by introducing multiple k values for the same n-bit word length. Instead of increasing code word quantity within a single k value, the system creates layered code spaces (k1, k2, ..., km) where each layer provides enhanced detection for specific error patterns, effectively using dimensional expansion to improve accuracy without linearly increasing total code words.
Solution Approach 2:
The patent performs preliminary error detection using simpler k1-out-of-n codes before applying more complex k2-out-of-n codes. This staged approach allows the system to quickly identify and correct obvious errors with fewer code words, then apply more sophisticated codes only when needed, reducing the effective number of code words required for high-accuracy detection.
3Manufacturing precision
If conventional error correction methods are used in RRAMs, then read times are long, but error correction accuracy is insufficient
Solution Approach 1:
The patent applies preliminary error detection and correction using k1-out-of-n codes before final verification with k2-out-of-n codes. This preliminary action identifies and corrects common error patterns early in the read process, reducing the need for time-consuming iterative correction and improving overall read speed while maintaining high accuracy.
Solution Approach 2:
The patent segments the error correction process into multiple stages, each using appropriate k-out-of-n codes for specific error types. This segmentation allows parallel processing of different error detection tasks, reducing total correction time while improving comprehensive error correction accuracy through specialized code application.
Data Source
AI summary
A solution for correcting errors is proposed, wherein a bit group of n memory cells is read and n states are determined therefrom, wherein the n states are determined in a time domain for a k1-out-of-n code and for a k2-out-of-n code, where k1 is less than k2. Furthermore, for a read n-bit word, which is a non-code word instead of a code word of the k2-out-of-n code, the previously read n-bit code word of the k1-out-of-n code is used to determine possible erroneous bits in the read non-code word. Possible code words of the k2-out-of-n code are determined for the non-code word based on the possible erroneous bits, and error correction is carried out using an external error code based on the possible code words.