Memory Error Rate Estimation Using Parity Violations
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Solution Overview
Problem
Memory devices, particularly flash memory, face errors due to mechanisms like read disturb, program disturb, and charge loss, which can cause threshold voltage changes, leading to incorrect data sensing and errors that existing error correction codes may not effectively mitigate.
Innovation Solution
Incorporating error rate estimation circuitry within the memory device to sense data, perform error detection operations, and estimate error rates based on parity violations, allowing for improved error correction, reduced complexity, and enhanced performance by mitigating errors and optimizing sensing voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction codes are used to mitigate memory errors, then data reliability is improved, but device complexity increases
Solution Approach 1:
The patent performs error detection operations and estimates error rates before executing full error correction codes. By preliminarily assessing the error situation using parity check operations and error rate estimation circuitry, the system determines whether full ECC processing is necessary, thereby reducing overall device complexity while maintaining data reliability when errors are present
Solution Approach 2:
Instead of always applying full error correction codes, the patent applies partial error detection and estimation actions first. The error rate estimation circuitry performs a subset of error detection operations (parity checks) to estimate error rates, and only initiates full ECC processing when the estimated error rate exceeds a threshold, thus avoiding excessive processing when errors are absent or minimal
2Measurement precision
If error detection operations are performed on sensed data, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The patent performs partial error detection operations by estimating error rates using a subset of parity check operations rather than examining every data bit in detail. The error rate estimation circuitry uses parity check results to estimate the overall error rate, providing sufficient measurement precision to determine whether full error correction is needed, while significantly reducing the time compared to comprehensive error analysis
Solution Approach 2:
The system uses feedback from error rate estimation to dynamically control the error correction process. The estimated error rate feeds back to the controller, which decides whether to initiate full ECC processing. This feedback mechanism allows the system to achieve accurate error detection precision only when necessary, optimizing the balance between measurement precision and processing time
3Reliability
If multiple parity check operations are performed to estimate error rates, then reliability is improved, but use of energy increases
Solution Approach 1:
The patent performs a limited number of parity check operations sufficient to estimate error rates rather than exhaustively checking all possible error conditions. The error rate estimation circuitry uses a predetermined number of parity checks to generate reliable error rate estimates, avoiding excessive energy consumption while maintaining sufficient reliability for determining whether full error correction is warranted
Solution Approach 2:
The system dynamically adjusts the number of parity check operations based on memory conditions and error patterns. The controller can modify the extent of error detection operations performed by the error rate estimation circuitry, changing operational parameters to balance reliability requirements against energy consumption constraints different memory regions or error scenarios
Data Source
AI summary
The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.