Memory Error Propagation via Cache Line Migration

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Solution Overview

Problem

Uncorrectable errors (UEs) in memory hardware degrade computer system performance, as existing error-correcting codes can detect but not correct these errors, leading to corrupted memory blocks that hinder system efficiency.

Innovation Solution

A method and system that detect corrupted memory blocks, migrate cache lines from the corrupted block to an uncorrupted one, generating an artificial error in the new block instead of copying the uncorrectable error, while maintaining the original layout, and replace the artificial error with error-free data when requested.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If uncorrectable errors are detected in memory blocks, then system reliability is improved by detecting errors, but system performance deteriorates due to inability to correct errors and degradation from corrupted memory blocks

Engineering Contradiction:
Improveerror detection capabilityVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The memory block is segmented into individual cache lines, and the error handling is applied at the cache line level rather than the entire memory block level. This allows partial migration where only corrupted cache lines are moved to new locations while clean cache lines remain in place, thereby maintaining better cache utilization and system performance while still handling errors reliably.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary error detection using ECC codes before errors propagate and cause system failures. By detecting uncorrectable errors early and initiating migration processes proactively, the system prevents performance degradation before it occurs, maintaining both reliability and productivity.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If corrupted memory blocks are migrated to new locations, then error propagation is prevented and reliability is improved, but system performance deteriorates due to migration overhead

Engineering Contradiction:
Improveerror propagation preventionVSAvoidmigration overhead
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

Migration is segmented at the cache line level rather than migrating entire memory blocks. Only cache lines containing uncorrectable errors are migrated to new locations, while clean cache lines remain in their original positions. This selective migration approach minimizes the overhead of the migration process while still preventing error propagation effectively.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The migration process applies local quality by treating each cache line differently based on its error status. Corrupted cache lines are migrated while clean cache lines are left in place, creating a heterogeneous memory layout that optimizes both reliability and performance by minimizing unnecessary data movement.

Inventive Principle:
Principle #3Local quality

3Reliability

If artificial errors are created instead of copying uncorrectable errors, then error propagation is limited and reliability is improved, but system complexity increases due to artificial error management

Engineering Contradiction:
Improveerror propagation limitationVSAvoidartificial error management
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The harmful uncorrectable error is extracted from the cache line and replaced with an artificial error marker. This extraction removes the actual error data that could propagate, while the artificial marker serves as a safe placeholder that can be managed by the system without causing error propagation, thus limiting error spread while maintaining manageable complexity.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

An artificial error acts as an intermediary between the detected uncorrectable error and the system's error handling mechanisms. Instead of directly copying the harmful error, the artificial error marker mediates the situation, allowing the system to track and handle errors in a controlled manner without propagating the actual uncorrectable error conditions.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Manufacturing precision

If cache lines are analyzed individually for errors, then manufacturing precision is improved by identifying specific corrupted lines, but processing time increases due to analysis overhead

Engineering Contradiction:
Improveerror identification precisionVSAvoidanalysis time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The memory block is segmented into cache lines that can be independently analyzed by ECC codes. This segmentation allows precise identification of which specific cache lines contain errors without needing to analyze the entire memory block, thereby maintaining high error identification precision while reducing the time required for error detection compared to block-level analysis.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9389973B2Memory error propagation for faster error recovery
Publication Date: 2016.07.12 ORACLE INT CORP
  • US9389973B2 patent drawing
  • US9389973B2 patent drawing
  • US9389973B2 patent drawing

AI summary

A method for managing a corrupted memory block. The method includes detecting the corrupted memory block, and removing, after detecting the corrupted memory block, references to the corrupted memory block. The method further includes identifying, after detecting the corrupted memory block, an uncorrupted memory block and analyzing each cache line. The method further includes determining, while analyzing each cache line, that a first cache line includes an uncorrectable error and creating, based on determining the first cache line includes the uncorrectable error, a second cache line including an artificial error, and migrating the second cache line to the uncorrupted memory block, where a layout of the corrupted memory block is maintained.