Memory System Error Analysis and Counter-Error Operations
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Solution Overview
Problem
Current memory systems rely on statistical error prediction methods, which result in low accuracy for anticipating serious errors, thereby degrading the overall reliability of the system.
Innovation Solution
A data processing system that includes a memory system with multiple memory devices, each equipped with error correction units and a host that analyzes error logs to determine error ranks and set appropriate error correction strengths, allowing for targeted counter-error operations to prevent serious errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If statistical error prediction methods are used, then the system can predict errors, but the accuracy of prediction is significantly degraded
Solution Approach 1:
The patent segments error prediction into multiple dimensions: error type segmentation (bit flip, coupling error, soft error), error location segmentation (specific memory addresses), and error severity segmentation. This multi-dimensional segmentation enables precise error prediction by analyzing patterns in each segment separately, thereby improving prediction accuracy while maintaining system reliability
Solution Approach 2:
The patent implements preliminary error prediction by continuously monitoring and analyzing error patterns before serious errors occur. The system maintains an error history database that records past errors, and uses this information to predict potential future errors, allowing preventive actions to be taken before system reliability is compromised
2Reliability
If error correction algorithms are applied to all memory devices, then errors can be corrected, but the device complexity increases
Solution Approach 1:
The patent applies local quality by implementing error correction selectively based on error ranks. Instead of uniform error correction across all memory devices, the system assigns different error correction strengths to different memory devices according to their error characteristics. High-risk memory devices receive stronger correction algorithms while low-risk devices use simpler methods, optimizing reliability without unnecessary complexity
Solution Approach 2:
The patent uses partial action by applying error correction only to the extent necessary. The error correction strength is adjusted based on error rank - some memory devices receive full error correction while others receive reduced or no correction. This partial application of error correction maintains system reliability for critical devices while reducing overall system complexity
3Reliability
If counter-error operations are performed on all memory devices, then serious errors can be prevented, but the loss of time increases
Solution Approach 1:
The patent applies local quality to counter-error operations by targeting only specific memory devices that have been identified as high-risk through error analysis. The system performs counter-error operations such as data migration, memory remapping, or enhanced monitoring only on memory devices with high error ranks, rather than applying these operations uniformly across all devices. This selective approach prevents serious errors in critical devices while minimizing time loss
4Measurement precision
If detailed error analysis is performed on all memory devices, then error patterns can be identified, but the loss of time increases
Solution Approach 1:
The patent applies local quality to error analysis by focusing detailed analysis only on memory devices that exhibit specific error patterns or have reached certain error thresholds. The system performs comprehensive error pattern identification on high-priority devices while using simplified monitoring on low-priority devices. This selective detailed analysis maintains high measurement precision for critical devices while reducing overall time loss
Data Source
AI summary
A data processing system comprising: a memory system comprising a plurality of memory devices, each of which comprises a first error correction unit and a plurality of cell array regions each having a plurality of memory cells coupled in an array to a plurality of word lines and a plurality of bit lines; and a host comprising a second error correction unit for correcting an error of data transferred from the memory system, and suitable for generating error correction information on the error correction operation of the second error correction unit, setting error correcting strengths to the respective memory devices using the error correction information and log information, and performing counter-error operations on the respective memory devices according to the error correcting strengths.