Memory Cell Error Rate Classification Using Adaptive Read Voltages
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Solution Overview
Problem
Conventional memory systems face challenges in accurately classifying the bit error rate of data retrieved from memory cells due to shifts in optimized threshold voltages caused by factors like charge loss and temperature variations, which affect data retention and reading accuracy.
Innovation Solution
A memory subsystem employing a binary classification decision tree technique uses compound features calculated from signal and noise characteristics measured at multiple optimized read voltages to classify the bit error rate, allowing for adaptive calibration and improved data retrieval operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional memory systems use fixed threshold voltages for reading data, then device complexity is reduced, but measurement precision of bit error rate classification deteriorates due to voltage shifts from charge loss and temperature variations
Solution Approach 1:
The patent implements dynamic threshold voltage adjustment by introducing a calibration circuit that continuously adapts read voltages based on measured signal and noise characteristics. Instead of using fixed threshold voltages, the system dynamically calibrates multiple read voltages (V1, V2, V3, V4) to track changes in memory cell characteristics caused by charge loss and temperature variations, thereby maintaining accurate bit error rate classification.
Solution Approach 2:
The patent employs feedback mechanisms where the calibration circuit measures signal characteristics (I1, I2, I3, I4) and noise characteristics from memory cells, then uses this feedback information to adjust and recalibrate threshold voltages. The system continuously monitors read currents at different voltages and adjusts the calibration parameters to optimize reading accuracy, creating a closed-loop control system that improves measurement precision.
2Measurement precision
If memory systems perform frequent calibration to maintain reading accuracy, then measurement precision improves, but productivity decreases due to additional calibration operations
Solution Approach 1:
The patent performs preliminary calibration operations during idle periods or during write operations before actual data retrieval is needed. The calibration circuit pre-adapts the threshold voltages to current memory cell conditions, so that when data reading is required, the system can use the pre-calibrated voltages without performing time-consuming calibration during the critical read path, thus maintaining both accuracy and productivity.
Solution Approach 2:
The patent implements periodic calibration cycles where the calibration circuit operates at scheduled intervals rather than continuously or on every read operation. The system performs calibration periodically to track drift in threshold voltages caused by charge loss and temperature changes, balancing the need for accurate reading with the requirement to maintain high data retrieval throughput by not calibrating on every operation.
3Reliability
If memory systems use multiple read voltages for calibration, then reliability of data retrieval improves, but loss of time increases due to multiple measurement cycles
Solution Approach 1:
The patent merges the calibration process with normal read operations by using the same read circuitry and signal paths for both calibration measurements and actual data retrieval. The calibration circuit uses the existing read currents (I1, I2, I3, I4) that would normally be used for data reading, combining multiple functions into a unified process that reduces the time penalty of calibration while maintaining reliability through multiple voltage measurements.
Data Source
AI summary
A memory sub-system configured to: measure a plurality of sets of signal and noise characteristics of a group of memory cells in a memory device; determine a plurality of optimized read voltages of the group of memory cells from the plurality of sets of signal and noise characteristics respectively; generate features from the plurality of sets of signal and noise characteristics, including at least one compound feature generated from the plurality of sets of signal and noise characteristics; generate, using the features, a classification of a bit error rate of data retrievable from the group of memory cells; and control an operation to read the group of memory cells based on the classification.