Semiconductor Memory Error Relief Circuit Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing bit errors and decreased yield in DRAM devices due to reduced fabrication design rules necessitate enhanced reliability in semiconductor memory devices, particularly in systems without error correction circuits.
Innovation Solution
Incorporating an error detection circuit and an error relief circuit with a replacement memory in semiconductor memory devices, which detects consecutive command sequences to identify and correct bit errors, reducing power consumption and processing overhead by eliminating the need for parity bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fabrication design rules are reduced to increase memory density, then memory capacity is improved, but bit error rate increases and yield decreases
Solution Approach 1:
The patent introduces a replacement memory as an intermediary component that mediates between the faulty main memory and the external device. When bit errors are detected in the main memory, the replacement memory provides substitute data, effectively mediating the error condition and maintaining system reliability without requiring changes to the fundamental memory cell structure or fabrication process.
Solution Approach 2:
The patent changes the operational parameters of the memory system by dynamically switching between main memory and replacement memory based on error detection. The system monitors bit error rates and adjusts its operation by activating the replacement memory when error thresholds are exceeded, thereby adapting to varying reliability conditions without altering the physical memory structure.
2Reliability
If error correction circuits are added to improve reliability, then bit error mitigation is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts the error correction functionality from the main memory array and places it in a separate replacement memory subsystem. This separation allows the main memory to remain simple while the replacement memory handles error mitigation, effectively removing the complexity burden from the primary storage path and reducing overall device complexity.
Solution Approach 2:
The replacement memory acts as a disposable resource that is activated only when errors occur. Instead of maintaining complex error correction circuits for all operations, the system uses a simpler replacement memory that is engaged only when needed, reducing average power consumption and device complexity while maintaining reliability when required.
3Measurement precision
If parity bits are stored in memory cells to detect errors, then error detection capability is improved, but storage capacity and manufacturing simplicity deteriorate
Solution Approach 1:
The patent segments the memory system into a main memory array for bulk data storage and a separate replacement memory for error mitigation. This segmentation allows the main memory to maintain full storage capacity without parity bits, while the replacement memory provides a dedicated error handling mechanism, effectively separating the storage function from the error detection function.
Solution Approach 2:
Instead of storing parity bits in the main memory cells, the patent uses the replacement memory to store substitute data that can replace erroneous data. This copying approach allows error detection and correction without consuming additional storage capacity in the main memory array, as the replacement memory contains redundant information that can be used when errors occur.
Data Source
AI summary
A semiconductor memory device including a memory cell array and an error relief circuit may be provided. The memory cell array includes plurality of memory cells which store data and are coupled to a plurality of word-lines and a plurality of bit-lines. The error relief circuit includes a replacement memory. The error relief circuit receives a command and an address from an external device, stores a first data associated with a first address in the replacement memory in response to detecting a sequence of the consecutively received commands with respect to the first address, and inputs/outputs the first data associated with the first address through the replacement memory.