Per-Row Memory Error Tracking for Post-Package Repair
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Solution Overview
Problem
Existing semiconductor memory devices lack comprehensive error correction mechanisms that provide transparency into error locations and recommend timely post-package repairs, leading to potential safety issues in applications like automotive systems.
Innovation Solution
Implementing a system to store per-row error information, including baseline and recent error data, and using an ECS circuit to analyze this data to recommend post-package repairs when necessary, ensuring timely remapping of defective rows and columns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction circuits scan every memory cell periodically to repair errors, then memory reliability is improved, but the system provides limited information on error correction and timing
Solution Approach 1:
The patent implements feedback mechanisms where error correction circuits provide status information back to the controller. Error status registers store and communicate error conditions, allowing the system to monitor and respond to error states. This feedback loop enables the controller to make informed decisions about when repairs are needed while maintaining memory reliability through periodic scanning and correction.
Solution Approach 2:
The patent introduces intermediary components including error status registers and recommendation circuits that mediate between the error correction scanning process and the controller. These intermediaries capture, store, and process error information, making it transparent to the controller without requiring direct access to the complex scanning mechanisms. This allows comprehensive error information to be provided while maintaining the reliability benefits of periodic error correction scanning.
2Reliability
If comprehensive error information is stored and analyzed, then repair recommendations can be provided, but device complexity increases
Solution Approach 1:
The patent segments error information storage and analysis into distinct functional components. Error status registers are divided into multiple fields (e.g., first field for error count, second field for repair status). Different circuits handle different aspects: some scan memory cells, others store error information, and still others generate repair recommendations. This segmentation reduces overall device complexity by distributing functionality across specialized, manageable components rather than requiring a single complex system.
Solution Approach 2:
The patent adds temporal and categorical dimensions to error information storage. Instead of storing only raw error data, the system stores error information across multiple dimensions: time (baseline vs. recent errors), severity (error counts), and status (repair recommendations). This multi-dimensional organization allows comprehensive error analysis while maintaining manageable complexity through structured, hierarchical data organization that can be processed systematically.
3Reliability
If post-package repair is performed timely based on error analysis, then collisions are reduced, but the system requires sophisticated error monitoring
Solution Approach 1:
The patent implements preliminary action by performing baseline error analysis during manufacturing testing before the memory device is shipped. Error status registers are pre-configured with baseline error information, and repair recommendations are generated in advance for known defective rows or columns. This preliminary error monitoring and repair planning reduces the need for complex runtime monitoring, as the system is already prepared with repair strategies before deployment, thereby reducing collisions while managing complexity through advance preparation.
Solution Approach 2:
The patent enables self-service error monitoring where the memory device autonomously tracks its own error conditions without requiring external intervention. Error status registers automatically update with error information from scanning operations, and recommendation circuits independently generate repair suggestions based on stored error data. This self-service capability reduces the sophistication required in external monitoring systems, as the memory device performs its own error analysis and repair planning, thereby reducing collisions while keeping overall system complexity manageable.
Data Source
AI summary
Per-row recent and/or baseline error information for word lines may be stored along the word lines in some examples. In some examples, baseline error information may be stored in a fuse array. In some examples, the baseline error information may be loaded from the fuse array to a memory array. In some examples, based on the recent and/or baseline error information, the memory device may provide a post-package repair recommendation.